JPH0554292B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a burst signal compensation circuit, particularly a TDMA
The present invention relates to a burst signal compensation circuit applied to a receiving system in a communication system based on the Time Division Multiple Access (Time Division Multiple Access) method.

Background of the Technology In the TDMA system, a single frequency band is shared by multiple communication stations in a time-sharing manner, and each communication station sends a burst to a pre-allocated time slot, or selects one of the multiple bursts to transmit. The process is to receive a burst corresponding to the time slot assigned to the time slot. These bursts form a series of frames, and similar frames appear repeatedly.

Such a TDMA system is suitable, for example, for a satellite communication system that communicates between a large number of ground stations via a satellite. In this case, because multiple ground stations transmit using separate frequency sources, the frequency of each burst signal varies from ground station to ground station. If such fluctuations occur, the error rate after demodulation deteriorates, so compensation measures are required to reduce the frequency error of the burst signal within each frame.

Prior Art and Problems FIG. 1 is a schematic diagram showing an example of a communication system using the TDMA method. The example in this figure shows a satellite link, which connects multiple ground stations 11-1 on Earth (E).
A, 11-B, 11-C... and 11-M are satellite 1
Communication is performed via 2. Note that 11-M is a master station and supervises slave stations 11-A, 11-B, 11-C, . . . .

FIG. 2 is a waveform diagram for explaining the transmission form of the TDMA system. In this diagram, A, B, C...
M is burst, and ground stations 11-A, 11-B, II
-C...11 -M represents the position of the time slots respectively occupied. If these series of bursts are one frame (F), many frames appear successively.

By the way, since the ground stations 11-A, 11-B, . . . are distributed over a wide area, it is difficult to completely synchronize the phases of each ground station, and therefore the frequencies of the respective burst signals are different from each other. Therefore, it is desirable that the demodulator in the reception system of each ground station compensate for frequency fluctuations individually and independently for each burst signal.

FIG. 3 is a block diagram showing the general configuration of the main parts of each ground station, and the present invention particularly relates to the demodulator (DEMOD) 36 in the lower receiving system. In this figure, data Din to be transmitted is multiplexed by a multiplexer 31, for example, using four-phase keying (PSK).
In the case of this method, a carrier wave Cr from an oscillator 34 is modulated by a modulator (MOD) 32 as two-channel data of in-phase and orthogonal components. Furthermore, the frequency is converted by an up converter (UP) 33 to the order of several tens of GHz, which is necessary for radiating toward the satellite, and then transmitted from the antenna AT.

On the other hand, the signal from the satellite is received by the receiving system antenna AT.
For example, the frequency is converted by a down converter (DOWN) 35 to the order of 140 MHz,
In the demodulator (DEMOD) 36, the recovered carrier C′r
After demodulating, the data Dout to be received is obtained from the demultiplexing device 37.

The demodulator in FIG. 3 uses each burst signal A, B, C...
In order to perform this reproduction correctly, it is necessary to individually and independently compensate for fluctuations in the transmission frequency for each burst signal, as described above. However, conventionally,
Detects the average frequency of all burst signals and applies AFC (Automatic Frequency Control) overall
The practice was to apply Although this conventional method appears to be a convenient burst signal compensation method, it has the drawback that it cannot compress frequency errors between burst signals. In particular, when the frequency difference between bursts is large, fluctuations between each burst cannot be suppressed within the range in which the demodulator can operate normally, resulting in bursts that cannot be demodulated or an increase in the data error rate. . This is the problem.

OBJECTS OF THE INVENTION In view of the above problems, an object of the present invention is to propose a burst signal compensation circuit that can individually and independently compensate for frequency fluctuations of each burst signal.

Structure of the Invention In order to achieve the above object, the present invention provides the nth(n
= 1, 2, 3...) The error of each burst signal frequency from the reference frequency in the previous frame is
This is characterized in that it is reflected in order to compensate for each burst signal frequency error in the (n+1)th frame.

Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 4 is a circuit diagram showing an embodiment of the burst signal compensation circuit according to the present invention. Further, FIG. 5 is a waveform diagram used to explain the overall operation of FIG. 4. In FIG. 4, a down converter 35, a demodulator 3
6. The separation device 37 and the like are as already explained. For example, each burst signal A, B, C, .
and frequency error detection section 41 (41-1 to 41-3)
is supplied to The carrier regeneration circuit 41-1 regenerates a reference carrier wave from the received signal, for example, a four-phase PSK signal, and supplies the regenerated reference carrier wave to the demodulator 36 and the subsequent AFC section (38, 42 to 46).

The demodulator 36 performs synchronous detection of the received signal using this reference carrier wave.

On the other hand, in the AFC section, first, the frequency error detector 41-2 detects the frequency of the reproduced carrier wave and the reference frequency.
A frequency error with Pr is detected. Note that here, the reference frequency Pr is the reference frequency generator 46.
It is supplied by more.

Next, a frequency/voltage converter 41-3 obtains a DC signal corresponding to the frequency error detected by the frequency error detector 41-2. Thereafter, unnecessary noise is removed by the low-pass filter section 42. This low-pass filter section 42 is composed of, for example, a CR filter,
The output changes as shown in column (2) of FIG. The column (1) in Figure 5 corresponds to the waveform in Figure 2, and Fn, F(n+
1) represents arbitrary nth and (n+1)th frames. The output from the low-pass filter section 42 is applied to one input of the adder 43, and added to the readout output from the storage section 44 applied to the other input. The reason for providing the adding section 43 is as follows. As described later, each burst signal A, B, C
In order to discharge the capacitor in the low-pass filter section 42 at every start point of..., the (n+1)th frame F _(o+1)
Burst signal A (burst signal B, C...
The output of the filtering unit 42 at the start point of the burst signal A (same also for the burst signals B, C, etc.) in the previous n-th frame F _o is reset to zero. This results in discontinuity with the output of the filtering section 42. So n
The output of the filtering unit 42 obtained at the end of the burst signal A (the same applies to the burst signals B, C, etc.) in the frame F o is stored in the storage unit 44 _, and At the start of the burst signal A (the same applies to burst signals B, C, etc.) at _(o+1 ), the stored output of the filtering section 42 is transferred to the wave section 42 at frame F _(o+1).
In addition to the output of , the burst signal compensation circuit is operated as if burst signal A (the same applies to burst signals B, C, . . . ) appears continuously. In this way, the above-mentioned adding section 43 adds the output of the filtering section 42 in the frame F _o stored in the storage section 44 to the output of the filtering section 42 in the frame F _(o+1) . The addition output from the addition section 43 is supplied to a storage section 44 on the one hand;
On the other hand, the frequencies of each burst signal P _A , P _B ,
Voltage controlled oscillator VCO4 for varying P _C ...
5, that is, inputted to the local oscillator as an oscillation frequency control signal. The output of VCO45 is
It is applied to the frequency converter 40 to finally change each burst frequency P _A , P _B , P _C . . . .

The storage unit 44 stores the addition output in the n-th frame F _o corresponding to each burst signal A, B, C, . . . and at the end point of each burst signal (E in FIG. 5).
Reference) Nearby, sampling and analog/digital converter 44-1 samples and stores as digital data in memory array 44-2. Note that the signal S _E representing the vicinity of the end point E of each burst signal is generated by the existing burst synchronization circuit 3.
8, this signal S _E triggers the sampling and analog/digital converter 44-1 and also activates the write enable terminal WE of the memory array 44-2. In this way, the vicinity of the end point E of each burst signal was captured as follows.
This is because the output of the low-pass filter section 42 (column (2) in FIG. 5) gradually rises or falls and becomes closest to a steady state in the vicinity thereof. The reason why the output gradually rises or falls in this way is due to the charging time constant of the capacitor provided in the filter section 42.

On the other hand, in the (n+1)th frame F _(o+1) , the memory array 44-2 corresponds to each burst signal and at the start point of each burst signal (S in FIG.
), the address decoder 44-3 reads out each addition output, and converts it to the digital/analog converter.
The analog readout output via 44-4 is added to the other input of the adder 43. At this point, the compensation control loop completes its cycle. The reason why the memory array 44-2 can be accessed in response to each burst signal is because the decoder 44-3 has a built-in counter _. Therefore, the address is +1
When the number of burst signals is counted, it is cleared to zero again, and the memory area corresponding to the first burst signal A is accessed again. This signal S _S triggers the digital/analog converter 44-4 and simultaneously discharges the capacitor in the filter section 42. In order to accurately detect the error amount for each burst signal, the capacitor must be discharged each time. Thus, the control voltage shown in column (3) of FIG. 5 is applied as an input to the VCO 45. As a result, the frequency fluctuations of the burst signals A, B, C, . . . in the n-th frame are reflected to compensate for each frequency in the (n+1)-th frame. When the frequency of each burst signal finally matches the reference frequency, the output of the filtering section 42 is zero, the data stored in the memory array is also zero, and the control voltage of the VCO 45 remains zero. It does not change.
That is, the VCO 45 oscillates at a predetermined frequency when the control voltage is zero, and maintains the output of the converter 40 at the reference frequency. If the error occurs and the frequency becomes higher than the reference value, data corresponding to the error is stored in the memory cell array 44-2, and the corresponding burst signal is
1) When it appears in the th frame, it is added to the error amount at that time (at the (n+1)th frame). If the error amount of this (n+1)th frame is positive, the addition output of the adder 43 takes a large positive value, and the frequency of the VCO 45 is further increased. Then the frequency of the output of converter 40 (equal to the difference between the frequency of the signal from down converter 35 and the frequency of the signal from VCO 45)
is significantly reduced.

Effects of the Invention As explained above, according to the present invention, frequency error compensation can be performed independently for each burst signal.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing an example of a communication system using the TDMA method, Fig. 2 is a waveform diagram to explain the transmission form of the TDMA method, and Fig. 3 shows the general configuration of the main parts of each ground station. FIG. 4 is a block diagram showing an embodiment of the burst signal compensation circuit according to the present invention, and FIG. 5 is a waveform diagram used to explain the overall operation of FIG. 4. 41...Frequency error detection section, 42...Low pass filter section, 43...Addition section, 44...Storage section, 45...
VCO, F, F _o , F _(o+1) ...Frame, A, B, C
...Burst signal, P _r ...Reference frequency, P _A , P _B ,
P _C ...Frequency of the burst signal, S...Start point of the burst signal, E... End point of the burst signal.

Claims (1)

[Claims] 1. A system that continuously receives frames consisting of a plurality of burst signals (A, B, C...M), compensates the reception frequency of each burst signal, and adjusts it to a predetermined reference frequency (Pr). AFC (Automatic
In a burst signal compensation circuit that performs Frequency Control, each frequency error between each received frequency and the reference frequency is converted into a frequency error signal having a voltage proportional to each frequency error, and the burst signal is a frequency error detecting section 41 that detects each of the frequency error detecting sections; a low-pass filter section 42 that includes a capacitor whose charging is started by the frequency error signal and outputs the charging voltage of the capacitor; and a first addition input and a second addition input; an adding unit 43 that sends out an addition output using the output from the band pass filter as the first addition input; and an addition output from the addition unit in the n-th (n=1, 2, 3...) frame. is sampled and stored in correspondence with each burst signal and near the end point of each burst signal, and the stored addition output is read out in the (n+1)th frame, and A digital storage section 44 that applies the voltage to the second addition input of the addition section at the start point, and a voltage controlled oscillator 45 that changes the frequency of each of the burst signals by receiving the addition output from the addition section as input. Characteristic burst signal compensation circuit.