JPH0554294B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a digital expansion/decoding circuit that can be used in PCM communications and digital recording reception or reproduction devices.

Conventional configurations and their problems Traditionally, linear quantization has been used in PCM communications and digital recording to increase the dynamic range with a limited number of bits due to constraints on communication paths and recording media. , Since the quantization accuracy changes instantaneously in broken line quantization and the SN ratio fluctuates,
A quasi-instantaneous companding method has been proposed that apparently improves this. In this quasi-instantaneous companding method, a unit time is determined in advance, and the data is compressed by setting the ratio so that the maximum value of the sample within that time does not overflow and has high accuracy, and is sent or recorded along with the range data. When receiving or reproducing data, the data is expanded and decoded according to the range. An example of a decoding circuit in this type of system is one that decodes m (positive integer) bits of digital data into an analog signal using an m-bit DA converter, and then decodes it by controlling an analog amplifier with variable amplification using range data. Although there is a method, it is necessary to increase the amplification degree of the amplifier corresponding to the range, and there are problems such as operating speed and noise.

On the other hand, another conventional example consists of a digital expansion circuit and a DA converter that obtains n bits of output from m bits of input and range data, and the expansion rule is to shift the m bits of input among the n bits of output and There was a method to fill the blank section with input MSB data. However, in this method, the blank portion that occurs at the bottom is discarded, so there is a considerable amount of error between the ranges.
There were drawbacks such as an offset value and a step at the range switching point.

Purpose of the Invention The present invention relates to an excellent digital expansion/decoding circuit that eliminates such conventional problems, and an object thereof is to minimize the offset value between each range and minimize the step at the range switching point. That is.

Structure of the Invention In order to achieve the above object, the present invention has the following features:
1, m<n, a positive integer, and when m and n, the range number is a digital expansion circuit that expands m-bit digital data with range data to n bits, and a DA converter having at least n bits; The expansion rule of the digital expansion circuit is to shift the input m bits to the bit position corresponding to the range among the output n bits.If a blank occurs on the upper bit side of the output n bits, the most significant bit of the input m bits is shifted. If a blank occurs on the lower bit side of the n bits of the output, the bit strings A and B shown below are required starting from the upper bit string. The present invention is characterized in that it is configured such that data of a certain length is extracted and used as bit string A-10000... bit string B-01111...

According to this configuration, the offset error between ranges can be eliminated by extension law 3, and the step can be minimized.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a block diagram of a digital expansion/decoding circuit in one embodiment of the present invention. In FIG. 1, 1 is a 3-bit digital data input terminal, 2 is a range data input terminal, 3 is a digital expansion circuit, 4 is a 6-bit DA converter, and 5 is an analog decoding output terminal. FIG. 2 is an input/output characteristic diagram based on the expansion law of the digital expansion circuit in one embodiment of the present invention. In FIG. 2, the horizontal axis represents decompressed data input, and the vertical axis represents analog output. The auxiliary vertical axis on the left side of FIG. 2 represents the analog output of each range.

The operation of the digital expansion/decoding circuit of this embodiment configured as described above will be explained below.
For simplicity, the number of ranges is set to three in this embodiment. First, explanation will be given based on FIG. The 3-bit digital data input from input terminal 1 and the range data input from input terminal 2 enter a digital expansion circuit 3 where they are digitally expanded and converted.
It is output as bit data. This 6-bit data is input to a 6-bit DA converter 6, converted into an analog signal and decoded, and a decoded output is obtained from an analog decoding output terminal 5.

In addition to the above basic operations, the operation of digital expansion conversion will be further explained based on FIG. There are three types of range data: range 0, range 1, and range 2. Range 0 is the most primitively encoded, and is designed to avoid clipping even when high-level signals are encoded. Range 1 and Range 2 are encoded by sequentially reducing the quantization size, so that quantization distortion can be reduced in small-level signals.
Note that the difference in quantization size between ranges is a power of 2, and the quantization size between range 0 and range 1 is twice as different. That is, decoding is performed by bit-shifting the input data in the output data according to the range.
In this embodiment, in range 0, the 3 input bits correspond to the upper 3 bits of the 6-bit length of the output, and in range 1, from the upper bit to the right.
In range 2, the upper bit is shifted 2 bits to the right to make it correspond. At this time, in range 1 and range 2, a blank is generated in the upper part, and one or two consecutive MSB bits of the input data are used for this blank. Also, blanks occur in all ranges on the lower side.
Therefore, the data of the required bit length is extracted from the upper part of the bit string 1000 and used as the lower blank. For example, when the input data is 110 and the range data is range 1, one blank is generated in the upper part, so this is used as the MSB of the input data, that is, 1, and the lower 2-bit blank is used as the upper 2 bits of the bit string 1000... Appropriate with 10. As a result, the expansion data is 111010
becomes.

Figure 2 shows the analog output of the DA converter 4, which obtains the expanded data in each range as described above and decodes it with two's complement. , Range 1 and Range 2 are shown. Note that the number written on the right side of the auxiliary vertical axis indicates the output voltage of the AD converter 6 decoded by two's complement, and for convenience of explanation, the minimum step is set to 1.

Figure 2d is a diagram that combines the input and output characteristics of each range. The vertical axis indicates analog output, and has the same scale as the auxiliary vertical axis. The horizontal axis is decompression data input.

As described above, according to this embodiment, the offset in each range can be made zero by allocating the bit string 1000 to the lower blank produced by the bit shift. As a result, the positive and negative amplitudes become equal and there is no offset error between the ranges, so there is no step at the range switching point. In other words, it is possible to minimize the occurrence of distortion in digital expansion decoding.

FIG. 3 shows a block diagram of a digital expansion/decoding circuit in another embodiment of the present invention.
In FIG. 3, the same components as in FIG. 1 are designated by the same numbers for simplicity. 3 differs from FIG. 1 in that a 5-bit DA converter 6 is used. The number of ranges is also 3, and they are exactly the same.

The operation of the digital expansion/decoding circuit configured as described above will be mainly explained with respect to the differences from the first embodiment. First, since the DA converter 6 has 5 bits, the data expanded by the digital expansion circuit 3 only needs to be 5 bits long, and even if it is 6 bits long, 1 bit on the LSB side can be discarded.

Therefore, similarly to FIG. 2, the input/output characteristic diagram based on the expansion law of the digital expansion/decoding circuit in this embodiment is as shown in FIG. In FIG. 4, the auxiliary vertical axes a and b are the same as those in FIG. 2, but the positive and negative balance of c is slightly uneven. This is because the lower-order blank of the expansion law no longer occurs, so the bit string 100 for adjusting the offset is no longer applied, and as a result, the offset shifts only in this range. Figure 4d is a diagram that combines the input and output characteristics of each range. For convenience, both the vertical and horizontal axes are on the same scale as in FIG.

As described above, according to this embodiment, the offset between ranges can be set to zero except for the smallest range, that is, range 2. That is, the step at the range switching point is minimized, and the occurrence of distortion in digital expansion decoding can also be minimized. Although the effects described above are slightly inferior to those of the first embodiment described above, the DA required for the configuration is
Only one bit of the converter and digital expansion circuit can be omitted. In particular, as the number of bits in a DA converter increases, high accuracy is required, which increases the technical difficulty as well as the price, so this has a significant economic effect.

In this example, the number of ranges is 3, the number of input data bits is 3, and the number of bits after expansion is 5 or 6, but these are positive integers > 1 and m < n, even if m and n. good.

Further, although the bit string assigned to the blank portion on the lower bit side is set to 1000..., the bit string 0111... may also be completely equivalent.

Effects of the Invention The present invention provides bit string A, that is, 1000... or bit string B, in the lower blank produced by performing digital expansion by shifting.
By allocating only the necessary bit length from the upper order of 0111..., the offset in each range can be made zero or the minimum, and as a result, the step phenomenon at the range switching point can be reduced,
The occurrence of distortion in digital expansion decoding can be minimized. Furthermore, by reducing the number of bits in the digital expansion circuit and DA converter, it is possible to realize an excellent digital expansion/decoding circuit that can produce a large economic effect at the cost of some sacrifice in characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital expansion circuit according to an embodiment of the present invention, FIG. 2 is an input/output characteristic diagram based on the expansion law of a digital expansion circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of a digital expansion circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of the digital expansion circuit in the embodiment of the present invention, and FIG. 4 is an input/output characteristic diagram based on the expansion law of the digital expansion circuit in another embodiment of the present invention. 1, 2...Input end, 3...Digital expansion circuit, 4, 5...DA converter, 5...Output end.

Claims (1)

[Claims] 1. Input compressed data of m bits obtained by compressing original data of n0 bits and compression range data,
It is equipped with a digital expansion circuit that obtains decoded data with a number of bits n (n is a positive integer) smaller than the above n0, and a DA converter with a number of bits n, and outputs m bits of input based on the expansion rule of the digital expansion circuit. Shift to the bit position corresponding to the range among the n bits of the output. If a blank occurs on the upper bit side of the n output bits, apply the most significant bits of the m input bits in series as many times as necessary to fill the blank. If a blank occurs on the lower bit side of the n output bits, extract the data of the required length from the upper bit of either bit string of the two bit strings A and B shown below and use it. A digital expansion decoding circuit characterized in that a string A-10000...a bit string B-01111...