JPH0556868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a circuit configuration for reducing test terminals when testing a large-scale, complex semiconductor integrated circuit.

[Conventional technology]

In recent years, due to remarkable progress in miniaturization technology for manufacturing semiconductor integrated circuits and demands for systemization, semiconductor integrated circuits have become larger in scale and more complex.

Generally, as the amount of circuitry integrated into one chip increases, the number of input/output terminals also tends to increase, and the number of pins increases as the scale increases. Accordingly, equipment for testing these semiconductor integrated circuits also tends to have a large number of pins, and is becoming very expensive.

Furthermore, the trend toward larger scale and more complex semiconductor integrated circuits has led to systemization in which functions that were conventionally divided into multiple chips are combined into one chip. For this reason, semiconductor integrated circuits have become more complex, such as wired (bus-connected) outputs of a plurality of functional units in their internal areas and bidirectional circuits.

The most common method for testing such semiconductor integrated circuits is the circuit division method, which is widely used.

In this method, the semiconductor integrated circuit 1 is divided into several functional units 4, 5, 6,
In this method, the chip is divided into 7 parts, and at the time of testing, the divided unit to be tested is directly controlled from the input/output terminals 2 and 3 of the chip.

A specific example using the circuit division method described above is shown in FIG. Signal line 4 existing at the boundary of the division unit in this example
0 has 3 circuits with division units 30 to 32.
One output circuit and two input circuits are connected. Now, focusing on division unit 30, when testing this division unit, put the output circuits of division units 31 and 32 into an impedance state, and
If it is in the output mode, the additional output circuit 60 is put into a high impedance state and the signal from the output circuit 20 is outputted to the output terminal 90 via the selector circuit 80 for testing.

Next, in the input mode, the output circuit 20 is in a high impedance state, so a test is performed by inputting a desired input signal from the input terminal 70 and supplying it to the input circuit 10 via the additional output circuit 60. .

On the other hand, during normal operation, the additional output circuit 60 needs to be electrically disconnected from the signal line 40, so the output is controlled to a high impedance state by the input terminal 71.

[Problem that the invention seeks to solve]

In the circuit configuration of the conventional test circuit described above, it is necessary to provide a terminal for controlling the output of the additional output circuit to a high impedance state on the signal line portion existing at the boundary of the division unit, which reduces the number of test signal terminals. It is increasing.

For this reason, a test device with a large number of pins is required, and an expensive test device is required, which has the disadvantage that economical testing cannot be performed. Furthermore, the chip size increases due to the increase in the number of required input/output terminals, and the number of input and output terminals that can be used for actual operation is limited because of the test signal terminals.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which an input circuit of an output circuit is commonly connected to a signal line, and an additional circuit is provided on the signal line, and the additional circuit includes a pull-up element or a pull-down element and a transistor. The transistor is connected in series between power supplies, and the connection point between the transistor and the pull-up element or pull-down element is connected to the signal line, and the transistor is connected in series between the normal operation and the output mode during testing. The signal output from the output circuit to the signal line is permitted by being held in a cut-off state, and during the input mode period during the test, the transistor is turned on and off, and the resulting change in the level of the signal line is reflected in the input mode. It is characterized in that it is used as an input signal to the circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.
Now, when testing the division unit 30 using the circuit division method, the outputs of the output circuits of the division units 31 and 32 are placed in a high impedance state and electrically disconnected from the signal line 40, and the division unit 30 is in the output mode. In this case, the output of the input signal additional output circuit 60 is also controlled to be in the OFF state by the input terminal 70, and the signal line 40 is
to the state where it is pulled up to the power supply V _DD . Since it is in output mode at this time, the signal line 40
becomes a state determined by the output circuit 20, and is detected by the external output terminal 90 via the selector circuit 80, and a test is performed.

Furthermore, when the division unit 30 is in the input mode, the output of the output circuit 20 is in a high impedance state, similar to the outputs of the output circuits of the other division units 31 and 32 connected to the signal line 40. Therefore, the input circuit 10
An input signal from an input terminal 70 is supplied to the input terminal 70 via an additional output circuit 60.

For example, when inputting a logical low level, the additional output circuit 60 is controlled to be in the on state, and conversely, when inputting a high level, the additional output circuit 60 is controlled to be in the off state, and the pull-up resistor 50 is connected to the signal line. 40 is set to a high level and is used as an input signal to the input circuit 10.

Next, during normal operation, the additional output circuit 60 must be electrically disconnected from the signal line 40 as in the conventional case, but if the additional output circuit 60 is controlled to be in the OFF state by the input terminal 70, the signal line 40 can be disconnected from the signal line 40. 40 is equivalent to being pulled up by a pull-up resistor 50, and there is no problem in normal operation at all.

〔Effect of the invention〕

As explained above, the present invention is capable of controlling on/off using an external signal and an element that is pulled up or pulled down to a signal line connecting a plurality of output circuits and one or more input circuits in an internal area of a semiconductor integrated circuit. By connecting the additional output circuit, there is an effect that the additional output circuit can be electrically disconnected except when necessary, without providing a test terminal for controlling the output of the additional output circuit to a high impedance.

As a result, the number of test terminals can be significantly reduced compared to conventional methods, and the number of pins on the test equipment can be reduced, making it possible to perform measurements with inexpensive test equipment, making it possible to perform economical tests. be.

Furthermore, when the chip size is determined by the number of input/output terminals, the chip size can be reduced by the reduction in the number of required terminals.

In addition, the number of test terminals can be reduced compared to the conventional method, and the number of terminals that can be used for signals for normal operation can be increased.

Incidentally, although the example shows the case of pull-up, it goes without saying that the same effect can be obtained even if pull-down is used.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
FIG. 2 is an explanatory diagram for explaining the circuit division method, and FIG. 3 is a circuit configuration diagram in conventional circuit division. 1... Semiconductor integrated circuit, 2... Input terminal group, 3
... Output terminal group, 4-7, 30-32 ... Division unit, 10 ... Input circuit, 20 ... Output circuit, 40
...Signal line, 50...Pull-up resistor, 60...
Additional output circuit, 70... input terminal, 80... selector circuit, 90... output terminal.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which an output circuit and an input circuit are commonly connected to a signal line, an additional circuit is provided on the signal line, and this additional circuit connects a pull-up element or a pull-down element and a transistor in series between power supplies. The connection point between the transistor and the pull-up element or the pull-down element is connected to the signal line, and the transistor is kept in a cut-off state during the normal operation and the output mode during the test. Signal output from the output circuit to the signal line is permitted, and during the input mode period during the test, the transistor is turned on and off, and the resulting level change on the signal line is used as an input signal to the input circuit. A semiconductor integrated circuit characterized by: