JPH0558652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an ultra-highly integrated semiconductor device in which the minimum wiring spacing of aluminum alloy wiring layers is 2 μm or less.

[Conventional technology]

Figure 2 shows, for example, "Electronic Integrated Circuits," Allison, McGraw-Hill Publishing, 1975.
Integrated Circuits, J. Allison, McGraw−
2 is a plan view showing the conventional semiconductor device shown in Chapter 1 (Hill, 1975, Japanese translation "Integrated Circuits", McGraw-Hill Kogakusha), and FIG. 3 is a cross-sectional view taken along the line A--A in FIG. 2. In FIGS. 2 and 3, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a wiring layer made of aluminum alloy (hereinafter referred to as "aluminum alloy wiring layer").

In a conventional semiconductor device, after forming transistors, capacitors, resistors, etc. necessary for an integrated circuit configuration on a semiconductor substrate 1 (these are not shown because they are unnecessary for explanation of the present invention), wiring is performed. A base insulating film 2 is formed, and contact holes (not shown) are formed in necessary parts. Thereafter, an aluminum alloy wiring layer 3 is formed over the entire structure to a thickness of 0.5 to 1.5 μm, and this aluminum alloy wiring layer 3 is patterned into a predetermined planar shape by photolithography.

The pitch and spacing of the aluminum alloy wiring layers 3 are important factors that determine the degree of integration of an integrated circuit, and the minimum processing dimensions achievable at the highest level of the current state of the art have been adopted. As a result, both the width and spacing of interconnects have now become less than 2 μm. Another factor that determines the width of wiring is current density. Due to the physical phenomenon called electro-migration, the current density flowing through the wiring is 1×
It is necessary not to exceed 10 ⁵ A/cm ² , and due to this restriction, power lines, ground lines, etc.
It has become necessary to increase the wiring width to 5 μm or more.

[Problem that the invention seeks to solve]

In conventional semiconductor devices, the aluminum alloy wiring layer is constructed as described above, but as a result of the rearrangement of atoms that occurs during annealing, the aluminum alloy wiring layer has the following properties as shown in FIGS. 2 and 3. ,
The wiring layer has a property of producing protrusions 3a called hills here and there. According to the inventor's experiments, this protrusion 3a sometimes has a height of 2 μm or more (extension in the width direction), and moreover, it often appears on both sides of wide wiring such as wiring width of 5 μm or more. It has the characteristic that it is almost never seen in thin wiring with a width of 2 μm or less.

If the height of the protrusions 3a as described above exceeds the spacing between the wires, for example, as schematically shown in FIG. produce defects.
For this reason, in conventional semiconductor devices, the wiring spacing is
Even if there was a technology to reduce the thickness to 2 μm or less, there was a problem in that it would be necessary to maintain a gap of 2 μm or more on both sides of wide wiring such as power supply lines and ground lines.

The present invention has been made in view of these points, and its object is to provide a highly reliable and highly integrated semiconductor device that is free from the possibility of short circuits between wiring lines due to blocks.

[Means for solving problems]

In order to achieve such an object, the present invention provides a semiconductor device having an aluminum alloy wiring layer with a wiring width of 5 μm or more, in which one end of the wiring layer is provided close to another wiring layer, and the wiring layer It is characterized in that a groove is formed separately from one end of the groove.

[Effect]

As in the present invention, by forming a groove at one end of the aluminum alloy wiring layer having a width of 5 μm or more, that is, at the side end facing the adjacent wiring layer, the occurrence of hillocks at the wiring side end can be completely eliminated. was experimentally confirmed. The following mechanism is considered to be the reason why the formation of grooves at the side edges of the aluminum alloy wiring layer prevents the occurrence of hillocks at the side edges.

In general, the occurrence of hillocks in aluminum alloys is a phenomenon based on the formation of grains in aluminum alloys and the relaxation mechanism of film stress. A transformation of Gree occurs. In particular, at the boundary between the free end of the membrane and the outside world, it is difficult for the force to prevent deformation to act, so deformation tends to concentrate, resulting in hillocks.

Therefore, when grooves are made at the side edges of the wiring layer as in the present invention, the aluminum in that area is partially divided into small grains, so stress from a wide range is locally concentrated. The mechanism itself that generates large hirotsuku no longer works. As a result, the occurrence of hock is almost completely suppressed. However, the necessary stress relaxation still needs to be carried out for the film as a whole, but with the structure of the present invention, significant movement of aluminum atoms due to stress relaxation does not occur at the side edges where the occurrence of hillocks should be prevented. , it is inevitable that the stress will be directed elsewhere.

In view of the above mechanism, the width of all aluminum alloy wiring layers used on the LSI pattern should be, for example, 2 μm or less, and areas where a large amount of current flows should be lined up in parallel with many wires, or wired in a mesh pattern using aluminum. Even cutting out part of the layer can help prevent cracks. However, such a configuration cannot be a practical solution because it involves significant area loss in terms of high integration, which is the first requirement for LSI patterns. This is because if an attempt is made to effectively achieve the same current path cross-sectional area using parallel thin wires or mesh wires, the area occupied by the wires will approximately double, which will significantly impede the improvement in the degree of integration.

In this regard, in the present invention, even if applied to a wiring layer with a width of several tens of micrometers, the loss of occupied area accompanying the application can be kept constant at most about a width of 0.5 micrometers (this is determined by the minimum pattern size). A feature is that area loss in pattern design can be minimized.

〔Example〕

An embodiment of a semiconductor device according to the present invention is shown in FIG. In Fig. 1, 3 is an aluminum alloy wiring layer, 3a is a hillock generated in the aluminum alloy wiring layer 3, and 4 is a wide aluminum alloy wiring layer 3 provided corresponding to a portion adjacent to another wiring layer. This groove 4 is formed parallel to and separated from one end of the aluminum alloy wiring layer 3. In this case, the width of the grooves 4 may be slightly smaller than the interval between the normal wiring layers, since it is acceptable for the grooves to have some degree of bridging.

In the conventional example, in a wide wiring layer having a width of 5 μm or more, hillocks were generated at both side edges. However, in this device, at least in a portion of such a wide wiring layer where adjacent wiring layers are close to each other, a groove 4 as shown in FIG. 1 is provided in a part of the adjacent wiring layer. Therefore, the side end facing the adjacent wiring layer has a structure similar to that of a narrow wiring layer, and there is no possibility that short circuits will occur due to hillocks between the wiring layers and the adjacent wiring layer. If the width of the groove 4 is wide, the actual area loss will be large, but in reality, the groove 4 does not need to be completely separated like in a normal aluminum wiring layer. It has been confirmed that the width can be much smaller than the minimum dimension as an integrated circuit pattern, since the purpose is simply to make it difficult for large movements of aluminum that would cause hillocks to occur during annealing. Therefore, the area loss due to providing the groove 4 can be extremely small.

In the above embodiment, the case where the grooves 4 are provided integrally over the necessary length is shown, but these may be provided in several areas, or one of the grooves may be provided in several areas. It goes without saying that the portion may be formed in the aluminum alloy wiring layer 3 so as to form an opening.

〔Effect of the invention〕

As explained above, in the present invention, by forming grooves along the side edges of an aluminum alloy wiring layer with a width of 5 μm or more, it is possible to prevent aluminum from moving during annealing and forming hills at the side edges. This has the effect of easily obtaining a semiconductor device having a high-density aluminum alloy wiring layer without any short-circuit failures with adjacent wiring layers.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a plan view showing a conventional semiconductor device, and FIG. 3 is a sectional view taken along the line A--A in FIG. 3... Aluminum alloy wiring layer, 3a... Hillock, 4... Groove.

Claims (1)

[Claims] 1. In a semiconductor device having an aluminum alloy wiring layer with a wiring width of 5 μm or more, one end of the wiring layer is provided close to another wiring layer, and a groove is formed at a distance from one end of this wiring layer. A semiconductor device characterized by: