JPH0713965B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an extremely high degree of integration in which an aluminum alloy wiring layer has a minimum wiring interval of 2 μm or less.

[0002]

2. Description of the Related Art FIG. 2 shows, for example, "Electronic Integrated Circuit, by Allison, published by McGraw-Hill, 1975" (Electronic Integ
Rated Circuits, J. Allison, McGraw-Hill, 1975, Japanese translation "Integrated circuit", McGraw-Hill Gakusha Co., Ltd.) FIG. 3 is a plan view showing the conventional semiconductor device shown in FIG.
FIG. 2 and 3, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a wiring layer made of an aluminum alloy (hereinafter referred to as "aluminum alloy wiring layer").

In a conventional semiconductor device, after forming transistors, capacitors, resistors and the like (which are not shown in the drawings because they are unnecessary for the description of the present invention) on the semiconductor substrate 1 after forming the integrated circuit. , The underlying insulating film 2 of the wiring is formed, and contact holes (not shown) are formed in necessary portions.
To form. Then, the entire aluminum alloy wiring layer 3
Is formed to a thickness of 0.5 to 1.5 μm, and the aluminum alloy wiring layer 3 is patterned into a predetermined plane shape by a photolithography method.

The pitch and spacing of the aluminum alloy wiring layer 3 are important factors that determine the degree of integration of the integrated circuit, and the minimum processing dimension that can be reached at the highest level of the technical level at that time has been adopted. As a result, at present, both the width and the spacing of the wiring have become 2 μm or less. Another factor that determines the width of the wiring is the current density. Due to the physical phenomenon called electro-migration, the current density in the wiring is 1 ×
It is necessary not to exceed 10 ⁵ A / cm ^2, and due to this restriction, it is necessary to widen the wiring width of the power supply line, the ground line, etc. to 5 μm or more.

[0005]

In the conventional semiconductor device, the aluminum alloy wiring layer is constructed as described above, and as a result of the rearrangement of the atoms that occurs during annealing in this aluminum alloy wiring layer, as shown in FIG. As shown in FIG. 3 and FIG. 3, protrusions 3 called hillocks are formed at various places in the wiring layer.
There is a property of generating a. According to an experiment by the inventor, the protrusion 3a sometimes has a height (extension in the width direction) of 2 μm or more, and often appears on both sides of a wide wiring such as a wiring layer of 5 μm or more. It has a characteristic that it is hardly seen in thin wiring with a width of 2 μm or less.

When the height of the projection 3a as described above becomes equal to or larger than the space between the wirings, as shown schematically in FIG. 3, for example,
An electrical short circuit occurs between the wirings, causing a fatal defect that the wiring does not operate as an integrated circuit. Therefore, in the conventional semiconductor device, even if there is a technique of setting the wiring interval to 2 μm or less, the width of the wide wiring such as the power supply line and the ground line must be set to 2 μm or more on both sides. There was a point.

In view of the above points, the present invention has been made to solve such a problem, and an object thereof is to achieve high reliability and high integration without the possibility of short circuit between wirings due to hillocks. To obtain the semiconductor device.

[0008]

In order to achieve such an object, the present invention provides a semiconductor device having an aluminum alloy wiring layer having a wiring width of 5 μm or more, wherein one end of the wiring layer is close to another wiring layer. It is characterized in that the wiring layer is provided with a concave and convex notch at one end.

[0009]

According to the present invention, the formation of hillocks at the wiring side end portion is completed by forming the uneven cuts at one end of the aluminum alloy wiring layer having a width of 5 μm or more, that is, at the side edge facing the adjacent wiring layer. It was confirmed experimentally that it would disappear. The following mechanism can be considered as a cause for preventing the hillocks from being generated at the side edges by making a notch at the side edges of the aluminum alloy wiring layer.

Generally, the generation of hillocks in an aluminum alloy is a phenomenon based on the formation mechanism of grains in the aluminum alloy and the relaxation mechanism of film stress. In order to relax the internal stress of the film and the stress applied from the outside through the passivation film and the like. , The transformation of the grain boundary occurs.
In particular, at the boundary between the film, which is the free end, and the outside world, it is difficult for the force to prevent deformation to act, so deformation is likely to concentrate, and as a result, hillocks occur.

Therefore, when a concave-convex cut is made in the side edge of the wiring layer as in the present invention, since the aluminum in that portion is partially divided into small grains, stress from a wide range is locally generated. The mechanism of concentrating and generating large hillocks itself does not work. As a result, the occurrence of hillocks is almost completely suppressed. However, the necessary stress relaxation still needs to be carried out for the entire film, but in the structure like the present invention, the side edges where it is desired to prevent hillock generation do not cause significant movement of aluminum atoms accompanying stress relaxation. , It goes without saying that stress goes to other places.

In view of the above mechanism, the LSI
The width of the aluminum alloy wiring layer used on the pattern is set to, for example, 2 μm or less, and in a portion where a large amount of current flows, many wirings are arranged in parallel, or a part of the aluminum wiring layer is cut out in a mesh shape. But it helps prevent hillocks. However, when such a configuration is adopted, a large area loss is involved in terms of high integration, which is the first requirement required for the LSI pattern, and this cannot be a practical solution. This is because, if it is attempted to realize substantially the same current path cross-sectional area with parallel thin wirings or mesh wirings, the area occupied by the wirings will almost double and the improvement in the degree of integration will be significantly impaired.

In this respect, according to the present invention, even if the present invention is applied to a wiring layer having a width of 10 μm, the loss of the occupied area due to the application can be kept constant at about 0.5 μm width (this is determined by the minimum pattern size). Therefore, the area loss in the LSI pattern design can be minimized.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a semiconductor device according to the present invention.
Shown in. In FIG. 1, 3 is an aluminum alloy wiring layer,
3a is a hillock generated in the aluminum alloy wiring layer 3,
Reference numeral 4 denotes a notch of a concavo-convex formed on the side edge of the wide aluminum alloy wiring layer 3 corresponding to a portion close to another wiring layer. In this case, the width of the notch 4 may be a little smaller than the usual distance between the wiring layers, because some bridges may be applied to each other.

That is, in the conventional example, the width is 5 μm.
In the wide aluminum alloy wiring layer as described above, hillocks were generated on both side edges. However, in the device of this embodiment, such a wide aluminum alloy wiring layer 3 is used.
Among them, at least in the portion where the adjacent wiring layers are close to each other, since the unevenness notch 4 as shown in FIG. 1 is provided in a part of the wiring layer on the adjacent side, the width at the side end facing the adjacent wiring layer is increased. The structure is similar to that of the thin wiring layer, and a hillock is not generated between the wiring layer and the adjacent wiring layer to cause a short circuit.

At this time, if the width of the notch 4 is wide, it is the same as the actual area loss is large. However, since the notch 4 makes it difficult for the aluminum to largely move during annealing to cause hillocks. Therefore, it has been confirmed that the width is much smaller than the minimum dimension of the integrated circuit pattern. Therefore, there is an advantage that the area loss due to the provision of the notch 4 can be extremely small.

[0017]

As described above, according to the present invention, the width is 5 μm.
By forming a concave-convex cut along the side edge of the aluminum alloy wiring layer of m or more that faces the adjacent wiring layer,
Since it is possible to prevent aluminum from moving at the time of annealing to cause hillocks on the side edges, it is possible to easily obtain a semiconductor device having a high-density aluminum alloy wiring layer without short-circuit failure with an adjacent wiring layer.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a plan view showing an example of a conventional semiconductor device.

3 is a cross-sectional view taken along the line AA of FIG.

[Explanation of symbols]

 3 Aluminum alloy wiring layer 3a Hillock 4 Notch

Claims (1)

[Claims] 1. A semiconductor device having an aluminum alloy wiring layer having a wiring width of 5 μm or more, wherein one end of the wiring layer is provided in the vicinity of another wiring layer, and an uneven cut is formed at one end of the wiring layer. A semiconductor device characterized by being provided.