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JPH0560655B2 - - Google Patents
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JPH0560655B2 - - Google Patents

Info

Publication number
JPH0560655B2
JPH0560655B2 JP60226541A JP22654185A JPH0560655B2 JP H0560655 B2 JPH0560655 B2 JP H0560655B2 JP 60226541 A JP60226541 A JP 60226541A JP 22654185 A JP22654185 A JP 22654185A JP H0560655 B2 JPH0560655 B2 JP H0560655B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
mold member
bonding
foamed resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60226541A
Other languages
Japanese (ja)
Other versions
JPS6285436A (en
Inventor
Shin Tada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60226541A priority Critical patent/JPS6285436A/en
Publication of JPS6285436A publication Critical patent/JPS6285436A/en
Publication of JPH0560655B2 publication Critical patent/JPH0560655B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 <技術分野> 本発明は半導体チツプを基板に取付ける方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a method of attaching a semiconductor chip to a substrate.

<従来技術> 半導体チツプの基板取付にあつて、半導体チツ
プをボンデイング方式で基板と接続する場合、当
該ボンデイング工程を終えて後、該半導体チツプ
のモールド(封止)工程を実施することになる
が、この様に、アセンブルにおいて2工程を必要
とすることは時間がかかり、コスト的に不利であ
る。
<Prior art> When attaching a semiconductor chip to a substrate, when the semiconductor chip is connected to the substrate by a bonding method, a molding (sealing) process for the semiconductor chip is performed after the bonding process is completed. As described above, requiring two steps in assembly is time consuming and disadvantageous in terms of cost.

<発明の目的> 本発明は、上記の事情に鑑み、ボンデイング工
程とモールド(モールデイング)工程とを同時に
行える様に改良された半導体チツプの基板取付方
法を提供することを目的とする。
<Object of the Invention> In view of the above-mentioned circumstances, an object of the present invention is to provide an improved method for attaching a semiconductor chip to a substrate so that a bonding process and a molding process can be performed simultaneously.

<実施例> 以下、本発明の構成を図面を参照しつつ述べ
る。
<Example> Hereinafter, the configuration of the present invention will be described with reference to the drawings.

本発明の半導体チツプの基板取付方法は、下記
の4工程から成つている。
The method of attaching a semiconductor chip to a substrate according to the present invention consists of the following four steps.

(A) 第1図に示す通り、LSI1を、該LSIチツプ
1のパツド2a,2bが形成された面を下にし
て、ボンデイング部材である異方性導電接着フ
イルム3を介して、基板(PWB)4上に載置
する。この際、該LSIパツド2a,2bが、
夫々、前記基板4上にパターン形成された導体
(銅)箔5a,5bに接続するべく位置合わせ
を行う。なお、この位置合わせは、COSダイ
レクトボンダーの様なプリズム方式若しくはカ
メラを2台用いた方式で実行される。
(A) As shown in FIG. 1, the LSI chip 1 is placed on the substrate (PWB ) 4. At this time, the LSI pads 2a and 2b are
Positioning is performed to connect to conductor (copper) foils 5a and 5b patterned on the substrate 4, respectively. Note that this positioning is performed using a prism method such as a COS direct bonder or a method using two cameras.

(B) 上記工程の結果、第2図に示される通り、前
記LSIチツプ1と前記基板4の仮止めがなされ
る。なお、第2図の各符号は既出のものと等価
である。(以上、第1工程) (C) 続いて、前記基板4上に載置されたLSIチツ
プ1上に、予め定量しておいた発泡樹脂5を滴
下する。第3図の通り、各符号は既出と同じ。
この発泡樹脂5はモールドのために使用される
ものである。
(B) As a result of the above steps, the LSI chip 1 and the substrate 4 are temporarily attached, as shown in FIG. Note that each symbol in FIG. 2 is equivalent to the one already mentioned. (Above, the first step) (C) Subsequently, a preliminarily measured amount of foamed resin 5 is dropped onto the LSI chip 1 placed on the substrate 4. As shown in Figure 3, each symbol is the same as previously mentioned.
This foamed resin 5 is used for molding.

この時点では、前記発泡樹脂5は、粘性のた
め、前記LSIチツプ上に留まつている。(以上、
第2工程) (D) 次に、前記発泡樹脂5が滴下されたLSIチツ
プ1上にボンダヘツド6を移動させ、該ボンダ
ーヘツド6を前記LSIチツプ1の上方から前記
基板4に向けて降下させる。
At this point, the foamed resin 5 remains on the LSI chip due to its viscosity. (that's all,
Second Step) (D) Next, the bonder head 6 is moved onto the LSI chip 1 onto which the foamed resin 5 has been dropped, and the bonder head 6 is lowered from above the LSI chip 1 toward the substrate 4.

すると、第2工程では前記LSIチツプ1上に
留まつていた発泡樹脂5が、該ボンダーヘツド
6に押圧され、流動していく。
Then, in the second step, the foamed resin 5 remaining on the LSI chip 1 is pressed against the bonder head 6 and flows.

このボンダーヘツド6は、前記LSIチツプ1
の高さと前記導電接着フイルム3の厚みに該発
泡樹脂5のモールド時の膜の厚さを加えた高さ
と、前記LSIチツプ1の長さに該発泡樹脂5の
モールド時の膜の厚さを加えた幅を備えてい
る。
This bonder head 6 is connected to the LSI chip 1.
, the thickness of the conductive adhesive film 3 plus the thickness of the foamed resin 5 when molded, and the length of the LSI chip 1 plus the thickness of the foamed resin 5 when molded. It has added width.

従つて、第4図にある通り、前記ボンダーヘ
ツド6が完全に被さつた状態になると、前記発
泡樹脂5は、前記LSIチツプ1と、前記LSIチ
ツプと前記基板4間に介在する前記導電接着フ
イルム3の周辺を包囲する。第4図の各符号は
既出のものと同じ。(以上、第3工程) (E) その後、前記ボンダーヘツド6に熱を加え
る。
Therefore, as shown in FIG. 4, when the bonder head 6 is completely covered, the foamed resin 5 covers the LSI chip 1 and the conductive adhesive film interposed between the LSI chip and the substrate 4. Surround the area around 3. Each symbol in Fig. 4 is the same as previously mentioned. (Above, third step) (E) After that, heat is applied to the bonder head 6.

この加熱の結果、前記導電接着フイルム3は
接着性を持ち、又、前記発泡樹脂5は体積を増
す。
As a result of this heating, the conductive adhesive film 3 has adhesive properties, and the foamed resin 5 increases in volume.

前記ボンダーヘツド6が上から押圧し、前記
基板4は固定台等で固定されているから、前記
LSIチツプ1は上方から押され、さらに前記導
電接着フイルム3は変形する。その結果、前記
LSIチツプ1と前記基板4が強固に接続され
る。(以上、第4工程) (F) 発泡樹脂5が硬化した後、前記ボンダーヘツ
ド6を取り外して、ボンデイング及びモールド
工程を終了する。第5図参照。なお、各番号は
既出のものと同じ。
Since the bonder head 6 presses from above and the substrate 4 is fixed with a fixing stand or the like,
The LSI chip 1 is pushed from above, and the conductive adhesive film 3 is further deformed. As a result, the above
The LSI chip 1 and the substrate 4 are firmly connected. (Fourth step) (F) After the foamed resin 5 is cured, the bonder head 6 is removed to complete the bonding and molding steps. See Figure 5. In addition, each number is the same as the one already published.

本実施例では、発泡樹脂5が加熱されて膨張
し、LSIチツプ1を基板4側に強く押すから、両
者の接続強度は大きい。
In this embodiment, the foamed resin 5 is heated and expands, and strongly presses the LSI chip 1 toward the substrate 4, so that the connection strength between the two is high.

<効果> 以上の様に本発明は、基板上に搭置された半導
体チツプ上に所定量の発泡樹脂よりなるモールド
部材を滴下し、モールド部材が滴下された半導体
チツプにボンダーヘツドを被せ、該モールド部材
を半導体チツプ及び該半導体チツプと基板間に介
在するボンデイング部材の周辺に流動させ、ボン
ダーヘツドによつて加熱を行うことでモールド部
材が膨張し半導体チツプを基板に強く押すので両
者の接続強度は大きく、ボンデイング部材による
接着とモールド部材の硬化を行う半導体チツプの
基板取付方法であり、半導体チツプが基板に密着
して硬化される状態にてボンデイング工程とモー
ルド工程とを同時に行うという効果が生ずるの
で、半導体を迅速に商品化、製品化でき、コスト
的に有利となる。
<Effects> As described above, in the present invention, a predetermined amount of a mold member made of foamed resin is dropped onto a semiconductor chip mounted on a substrate, a bonder head is placed over the semiconductor chip on which the mold member has been dropped, and the bonder head is placed on the semiconductor chip mounted on a substrate. The material is flowed around the semiconductor chip and the bonding member interposed between the semiconductor chip and the substrate, and heated by the bonder head, which causes the mold member to expand and strongly press the semiconductor chip against the substrate, increasing the strength of the connection between the two. , is a method for attaching a semiconductor chip to a substrate by adhering with a bonding member and curing a molding member, and the effect is that the bonding process and the molding process are performed simultaneously while the semiconductor chip is hardened in close contact with the substrate. Semiconductors can be quickly commercialized and manufactured, resulting in cost advantages.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第5図は、本発明に係る半導体チツ
プの基板取付方法の工程図である。 1……LSIチツプ、3……異方性導電接着フイ
ルム、4……基板、5……発泡樹脂、6……ボン
ダーヘツド。
1 to 5 are process diagrams of a method for attaching a semiconductor chip to a substrate according to the present invention. 1... LSI chip, 3... Anisotropic conductive adhesive film, 4... Substrate, 5... Foamed resin, 6... Bonder head.

Claims (1)

【特許請求の範囲】 1 半導体チツプを基板に取付ける方法であつ
て、 半導体チツプをボンデイング部材を介して基板
上に搭置する工程、 前記基板上に搭置された半導体チツプ上に所定
量の発泡樹脂よりなるモールド部材を滴下する工
程、 前記モールド部材が滴下された半導体チツプに
ボンダーヘツドを被せ、該モールド部材を前記半
導体チツプ及び該半導体チツプと前記基板間に介
在するボンデイング部材の周辺に流動させる工
程、 前記ボンダーヘツドによつて加熱を行うことで
前記モールド部材が膨張し前記半導体チツプを前
記基板に圧接しつつ、前記ボンデイング部材によ
る接着と前記モールド部材の硬化を行う工程と からなることを特徴とする半導体チツプの基板取
付方法。
[Scope of Claims] 1. A method for attaching a semiconductor chip to a substrate, comprising the steps of: placing the semiconductor chip on the substrate via a bonding member; foaming a predetermined amount on the semiconductor chip placed on the substrate; a step of dropping a mold member made of resin, a step of covering the semiconductor chip onto which the mold member has been dropped with a bonder head, and flowing the mold member around the semiconductor chip and the bonding member interposed between the semiconductor chip and the substrate. The method is characterized by comprising the steps of performing bonding with the bonding member and curing the mold member while the mold member expands by heating with the bonder head and presses the semiconductor chip against the substrate. How to attach a semiconductor chip to a board.
JP60226541A 1985-10-09 1985-10-09 Mounting method for semiconductor chip on substrate Granted JPS6285436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60226541A JPS6285436A (en) 1985-10-09 1985-10-09 Mounting method for semiconductor chip on substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60226541A JPS6285436A (en) 1985-10-09 1985-10-09 Mounting method for semiconductor chip on substrate

Publications (2)

Publication Number Publication Date
JPS6285436A JPS6285436A (en) 1987-04-18
JPH0560655B2 true JPH0560655B2 (en) 1993-09-02

Family

ID=16846762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60226541A Granted JPS6285436A (en) 1985-10-09 1985-10-09 Mounting method for semiconductor chip on substrate

Country Status (1)

Country Link
JP (1) JPS6285436A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101983419B (en) * 2008-04-04 2012-08-08 索尼化学&信息部件株式会社 Semiconductor device and method for manufacturing the same
JP5253127B2 (en) * 2008-12-15 2013-07-31 トッパン・フォームズ株式会社 Mounting method of semiconductor chip

Also Published As

Publication number Publication date
JPS6285436A (en) 1987-04-18

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Legal Events

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EXPY Cancellation because of completion of term