JPH0561671B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field]

In the present invention, the main CPU is a general-purpose CPU, and the sub
CPU has external memory access function
This relates to a multiprocessor system using a single-chip CPU that does not have a WAIT function. Note that the general-purpose CPU referred to in the present invention refers to a bus output from the CPU that includes ROM, RAM, and
Refers to a system that combines I/O, peripheral chips, etc., such as Intel's 8080,
8086 and Zilog Z80 are applicable. A single-chip CPU as used in the present invention is one that has a CPU, ROM, RAM, and I/O functions on a single chip.The terminals of the chip are I/O ports, and the external memory access function is usually not available. Although some devices do not have this function, some devices do have an external memory access function using an I/O port (for example, the Intel 8051).

[Conventional technology]

In a multiprocessor system, a system in which access timing to a shared memory is assigned in advance to each processing device is known, as shown in Japanese Patent Laid-Open Nos. 51-11534 and 1987-27353. In the former method, memory access time is time-divided and allocated to each CPU in advance, regardless of instruction execution, using a signal having a constant period. The latter generates a synchronization signal and eliminates simultaneous accesses in order to prevent one processor from being put on hold and reducing throughput when the shared memory is accessed simultaneously. Note that the problem with the latter is a decrease in throughput of several hundreds of nanoseconds only during memory access, but the problem in this application is several tens of microseconds, which is a completely different technology. The present applicant proposed a system in which the allocation is not made in advance but is synchronized with the execution of processing, in the patent application filed in 1983
-91454 (Special Publication No. 63-63941). This proposal directly connects a common bus between a 1-chip CPU, a general-purpose CPU, and an external memory, and when processing data, the general-purpose CPU occupies the bus and processes the data, and when transferring data, the 1-chip CPU compared to the general-purpose CPU
The configuration was such that a HOLD request was issued to cause the general-purpose CPU to abandon the bus, and the one-chip CPU occupied the bus. An example of transferring 16 bytes of data from address "FF00H" in RAM to address "30H" in the internal memory of a 1-chip CPU (that is, sequentially outputting RAM data) will be explained. First, if we were to create a program ignoring the general-purpose CPU, we could consider the program shown in Figure 1. However, in reality, a general-purpose CPU may access RAM, so a single-chip CPU may access RAM.
When executing an instruction (MOVE A, @DPTR) that accesses the 1-chip CPU, it is necessary to establish bus occupancy for the 1-chip CPU.

[Problem to be solved by the invention]

However, in such systems, when the general-purpose CPU is temporarily inactive, the general-purpose CPU remains on HOLD, so if the number of bytes of data transfer is large, the execution speed will drop significantly, and only inefficient processing will be performed. It became clear that it could not be done. Therefore, the present invention solves the above problems, and when a single-chip CPU accesses shared memory, a general-purpose
General purpose only when the CPU accesses this at the same time
The purpose of the present invention is to provide a multiprocessor system that can prevent a decrease in the execution speed of a general-purpose CPU by only applying WAIT to the CPU.

[Means to solve the problem]

The present invention includes at least (a) a general-purpose CPU having a bus for outputting to the outside, (b) a shared memory, and (c) normally accessing its own internal memory, and performing input/output only when accessing the shared memory. The CPU is a one-chip CPU with a bus output to a port, and the shared memory is accessed at a fixed time interval, and a dummy instruction that causes a read or write to occur before that time interval, and a dummy instruction that causes the read or write to occur after that dummy instruction, and 1 with the function of issuing commands to periodically access shared memory
(d) a bus buffer that connects a one-chip CPU side bus to which the shared memory and input/output ports of the one-chip CPU are connected, and a general-purpose CPU side bus to which peripheral chips, etc. accessed by the general-purpose CPU are connected; (e) The one-chip CPU periodically accesses the shared memory by outputting a pulse with a predetermined time width after a predetermined time after a read command or write command to the shared memory by the one-chip CPU is generated. transmits the read command or write command signal to the shared memory at regular intervals, and immediately before transmitting a signal to disconnect the bus buffer;
a timing generator that issues a WAIT signal to the general-purpose CPU when the CPU issues a chip select signal to access the shared memory at the time when the pulse of the predetermined time width is being output; The pulse of the predetermined time width is more general-purpose than the time when one chip CPU accesses the shared memory.
The system is characterized in that it has enough time to start up before the shared memory access time of the CPU.

[Effect]

The general-purpose CPU bus includes ROM, RAM, and even
A system is constructed by connecting I/O, peripheral chips, etc., but in the present invention, it is also connected to the bus on the 1-chip CPU side via a bus buffer, and the 1-chip CPU
Shared memory connected to the side bus can also be accessed. The bus of a single-chip CPU is normally an input port, and becomes a bus only when accessing shared memory. Therefore, just before the 1-chip general-purpose CPU accesses the shared memory, the 1-chip general-purpose CPU
All you need to do is establish bus exclusive rights (separate the general-purpose CPU from the shared memory bus and make the general-purpose CPU wait). To this end, we added a relatively simple circuit called a timing generator, and added dummy instructions (original 1-chip
The present invention uses an instruction that generates a write or read instruction the same time interval as the CPU access cycle. As a result, just before the CPU of one chip accesses the shared memory, the bus connecting the general-purpose CPU and the shared memory is disconnected.
The chip CPU can occupy the shared memory only for the time required for access. When one chip CPU accesses the shared memory, the general-purpose
CPU processing has finished and there is no problem.

【Example】

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of a circuit constituting the present invention. In the figure, 1 is a one-chip CPU (for example, Intel 8051) that has the function of accessing shared memory (RAM) 2, and 3 is a timing signal. The generator 4 is a bus buffer between the bus 5 on the general-purpose CPU side and the bus 6 on the 1-chip CPU side, and 9 is a priority discrimination circuit. Incidentally, an example of the internal circuit of the timing signal generator 3 is shown in FIG. 3-a is monostable multivibrator, 3-b
is a buffer that transmits read or write commands from the 1-chip CPU to the shared memory. Now, similar to the operation example described above, we will start with one chip from address “FF00H” in the shared memory.
The case of transferring 16 bytes of data to address "30H" of the internal memory of CPU 1 (ie, reading RAM data) will be explained. FIG. 4 shows a 1-chip CPU program that executes this operation. The command shown in A in the figure (MOVX
A, @DPTR), the 1-chip CPU issues an RD signal and tries to read the data from the shared memory, but the RD signal is stopped by the timing signal generator 3, and the shared memory 2 is not accessed. However, the timing signal generator 3 is activated by this instruction A, and as shown in FIG.
7μsec (i.e. program loops and RAM
The timer of 2μsec (reading period) and 2μsec (that is, the execution time of the readout program) operates sequentially, and "MOVX A, @DPTR" shown in B in Figure 4
Immediately before the execution of , the SEL signal shown at 7 in FIG. 2 is generated. Therefore, when the bus buffer 4 is disconnected and the general-purpose CPU attempts to access the shared memory 2, a WAIT signal is sent and the general-purpose CPU
Make the CPU look forward to it. In other words, the first instruction A is a dummy instruction, and is an instruction for establishing bus occupancy of one chip CPU before instruction B, which is actually executed. FIG. 6 shows the relationship among the dummy instruction, the instruction that actually accesses the shared memory 2, and the output of the timing signal generator. That is, the purpose of the dummy instruction is to generate a read or write instruction in LOOP by the same time interval as the original one-chip CPU access cycle. After 7μs after a read or write command is issued, the timing signal generator 3
Outputs a 2μs pulse. The access time for a general-purpose CPU to shared memory is approximately 100 ns, and 1
It has enough time to start up before the shared memory access time of the general-purpose CPU than the time when the chip CPU accesses the shared memory, so by the time one chip CPU accesses the shared memory, the general-purpose CPU's processing has finished. There are no bus collisions. With this, shared memory 2 is 1 chip.
It occupies only 2 μsec when the CPU accesses it, and data can be read. The last command in Figure 4 “CJNE R0, #40H
LOOP” to return to command B and repeat this 16 times (∵
40H−30H=10H, i.e. 16) Repeat, 16
Transfer bytes of data. In other words, the conventional example shown in Fig.
91454), processing time per loop is 128μsec
(8 μsec x 16), one chip CPU occupies the bus and stops the general-purpose CPU, whereas in the present invention, the occupation time per loop is 2 μsec x 16 =
It only occupies shared memory for 32μsec. Also, as long as the general-purpose CPUs do not attempt to access shared memory at the same time, the operation of the general-purpose CPUs is not hindered. To explain using FIG. 2, the signal 7 from the timing signal generator 3 is input to the priority determination circuit 9, and if it is not being accessed from the general-purpose CPU, the bus buffer 4 is immediately disabled and the general-purpose
Separate the CPU bus and shared memory. At this time, if there is an access from the general-purpose CPU, the general-purpose
Apply WAIT to the CPU. If the general-purpose CPU is accessing, disconnection occurs when the access is completed. Although reading has been described above, writing is also the same. Furthermore, the timing signal generator 3 can be implemented using a counter or other circuit element as long as it executes the time chart shown in FIG. 5, even if the monostable multivibrator is not used as in the circuit example shown in FIG. It can also be composed of

【Effect of the invention】

As described above, according to the present invention, one chip
Since the time that the CPU occupies shared memory can be reduced, it is possible to provide a system with high processing efficiency for the main general-purpose CPU. In particular, by having a single-chip CPU perform communication processing, for example, the load on the main CPU can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is an example of a conventional program, FIG. 2 is a specific embodiment of the present invention, FIG. 3 is an example of the internal circuit of the timing signal generator of the present invention, FIG. 4 is a program of the present invention, and FIG. 5 is a program example of the present invention. Time chart of the present invention, No. 6
The figure is a diagram showing the relationship between commands and operations of the present invention. 1...1 chip CPU, 2...shared memory,
3...timing signal generator, 4...bus buffer, 9...priority discrimination circuit.

Claims (1)

[Claims] 1. At least: (a) a general-purpose CPU having a bus that outputs to the outside, (b) a shared memory, and (c) normally accessing its own internal memory, and when accessing the shared memory. 1-chip CPU with bus output only to input/output ports
The shared memory is accessed at a fixed time interval, and includes a dummy instruction that causes a read or write to occur earlier by that time interval, and an instruction that actually periodically accesses the shared memory after the dummy instruction. (d) a 1-chip CPU side bus to which the shared memory and input/output ports of the 1-chip CPU are connected, and a general-purpose CPU side to which peripheral chips, etc. accessed by the general-purpose CPU are connected; (e) After a predetermined time after a read command or write command to the shared memory of the one-chip CPU is generated, the one-chip CPU outputs a pulse of a predetermined time width, so that the one-chip CPU reads the shared memory. transmits the read command or write command signal to the shared memory every fixed period of periodic access to the shared memory, and immediately before that, issues a signal to disconnect the bus buffer;
a timing generator that issues a WAIT signal to the general-purpose CPU when the CPU issues a chip select signal to access the shared memory at the time when the pulse of the predetermined time width is being output; The pulse of the predetermined time width is more general-purpose than the time when one chip CPU accesses the shared memory.
A multiprocessor system characterized by having enough time to start up before the shared memory access time of a CPU.