JPH0562791B2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to the control of I/O command output that instructs a CPU to read/write to external registers, external storage devices, etc. (hereinafter referred to as devices), and in particular, The present invention relates to a command output control method for using devices that require read/write recovery time.

(Prior Art) Generally, in order to access the same device, a certain amount of time, ie, read/write recovery time, is required from the previous access to the next access. Traditionally, the read/write required for each device is
Write recovery time was obtained by adjusting the timing for each device using firmware.

(Problems to be Solved by the Invention) In the conventional I/O command output control method described above, the necessary timing relationships are established by firmware, so if the performance or speed of the CPU changes, firmware There was a drawback that it also had to be re-created.

An object of the present invention is to detect an I/O command, activate a plurality of timer circuits using the output of an I/O address decoding circuit, and then activate a plurality of timer circuits based on the output of an I/O address decoding circuit, and to synchronize the command status signal output from the CPU with the timer circuits set in the plurality of timer circuits. The output timing of the I/O command is determined according to the value and the output of the I/O address decoding circuit, and the I/O command is sent to the bus signal line according to the output timing instruction and the value of the command status signal. The object of the present invention is to provide an I/O command output control method that eliminates the above drawbacks by outputting O commands and eliminates the need to recreate firmware for different types of CPUs. .

(Means for Solving Problems) The I/O command output control method according to the present invention includes a plurality of timer circuits, an I/O address decoding circuit, a timer control circuit, a command control circuit, and a command output circuit. It is constructed with the following features.

The multiple timer circuits are for counting time, the I/O address decoding circuit is for decoding I/O addresses, and the timer control circuit is for counting multiple times using the output of the I/O address decoding circuit. This is for starting one of the timer circuits.

The command control circuit receives a command status signal indicating the type of command output from the CPU,
This is for determining the output timing of an I/O command based on the values set in a plurality of timer circuits and the output of the I/O address decoding circuit.

The command output circuit is for outputting an I/O command to the bus signal line according to the command status signal and instructions from the command control circuit.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the I/O command output control method according to the present invention. In FIG. 1, 11 to 13 are timer circuits, 2 is a command control circuit, 3 is a timer control circuit, 4 is a command output circuit, and 5 is an I/O address decode circuit.

In FIG. 1, the command output circuit 4 is a CPU
Based on the data value output from the command bus signal line 4a to the command status signal line 10a.
It outputs commands on top of the . The I/O address decode circuit 5 uses the address bus signal line 12
The address information value on I/O decode signal line 5a is decoded and the decoded result is output onto I/O decode signal line 5a.

The timer control circuit 3 has a command bus signal line 4a.
The I/O command is detected and the timer circuit to be activated via the I/O decode signal line 5a is determined. The timer circuits 11 to 13 all operate according to instructions from the timer control circuit 3.
The timer control signal line 3a is a source for sending control information from the timer control circuit 3 to the timer circuits 11-13. The timeout signal line 1a is connected to the timer circuit 11~
13 outputs a timeout signal. The command control circuit 2 receives a command status signal sent from the CPU to the command status signal line 10a, a timeout signal sent from the timer circuit 1 to the timeout signal line 1a, and an I/O signal sent to the I/O decode signal line 5a. The command output timing is determined by the decode signal, and the timing at which the wait request signal is sent to the CPU via the traffic light 11a is determined by the above process. At the same time, the command output timing is transmitted from the command control circuit 2 to the command output circuit 4 via the command control signal line 2a.

FIG. 2 is a timing chart showing an example of the operation shown in FIG. 1 described above.

In FIG. 1, there are three timer circuits 11 to 13.
The I/O decode signal decoded by the I/O address circuit 5 is also divided into three blocks and decoded. Further, three blocks of the I/O decoded signal are respectively referred to as an A block, a B block, and a C block, and each timer circuit 11 to 13 is sequentially assigned to each block.

Next, the reason for dividing into blocks in this way will be explained using an example.

Generally, in order to access the same device, a certain amount of time (read/write recovery time) is required from the previous access to the next access. (hereinafter referred to as RAM)
Considering the case where three devices are connected to the CPU by the circuit (or device) according to the embodiment of the present invention, accesses are made at intervals longer than the recovery time, such as register a → RAM → register c... There is no problem if it is done in register a → RAM address 0 →
When an access is performed such as from address 1 of RAM to register c, it is particularly necessary to provide an interval longer than the recovery time between accessing address 1 of RAM after accessing address 0 of RAM. in this case,
In this embodiment, for example, block A is set to register a,
Block B corresponds to all the addresses of one chip's RAM (if there are RAMs from different chips, it becomes a different group), block C corresponds to register c, and so on, the RAM and register a as seen from the CPU,
The entire access space of c is divided into blocks.
Timer circuits 11, 12, 1 corresponding to each block
3, it is monitored whether the read/write time has elapsed since the previous access to the same block. For example, the timer circuit 11
is activated immediately after the command of block A is output from the command output circuit, sets the timeout signal to 0, and returns the timeout signal to 1 after the recovery time has elapsed. If an I/O command belonging to block B is supplied before the timeout signal of block A is output, the timeout signal from the timer circuit of block B has already become "1", so the command is sent to block B. The command is immediately output from the command output circuit 4, and at the same time, the timer circuit 12 of block B is started, and the block B
The timer circuit output becomes "0" and this continues for the recovery time. If an I/O command indicating access to block B is supplied again within this recovery time, since the timer circuit output of block B is "0", a wait request signal is sent from the command control circuit 2 to the CPU. The wait request signal is released when the timeout signal of block B becomes "1", and the command corresponding to the second access to block B is output from the command output circuit 4.

In this manner, the present invention prevents I/O commands to the same device from being output multiple times within the recovery time by dividing the address space that can be accessed by the CPU into blocks.

1 and 2, when the timer control circuit 3 detects the end of the I/O command sent on the command bus signal line 4a, the timer control circuit 3 detects the state on the I/O decode signal line 5a. I'm going to investigate. At this time, the address bus signal line 12a
Assuming that the address in the A block is output in the I/O address decode circuit 5,
"1" is output to the bit corresponding to the A block of the O decode signal line 5a. The timer control circuit 3 is
The current I/O is determined by the value of the I/O decode signal line 5a.
When it is determined that the O access is to the A block, the timer circuit 11 is instructed to start.

Therefore, the timer circuit 11 immediately outputs "0" to the timeout signal line 1a to start measuring time, and when the designated time comes, returns the timeout signal line 1a to "1". When the CPU requests output of an I/O command via the command status signal line 10a, the command control circuit 2 immediately checks the state of the I/O decode signal line 5a.
The state of the corresponding timeout signal line 1a is checked. At this time, it is assumed that the state of the I/O decode signal line 5a indicates the B block. Therefore, if the state of the timeout signal line 1a is "1", command output permission is immediately given to the command output circuit 4 via the command control signal line 2a. Furthermore, if the state of the timeout signal line 1a is "0", the command control circuit 2 immediately sends a wait request to the CPU via the wait request signal line 11a, and sends a wait request to the command output circuit via the signal line 2a. A command output disallowance signal is sent to 4.

After that, when the state of the timeout signal line 1a becomes "1", the command control circuit 2
Release the wait request that was output to the CPU,
A command output permission signal is sent to the command output circuit 4 via the signal line 2a. When command output permission is received from the command control signal line 2a, the command output circuit 4 outputs the command status signal line 1.
A command is sent to the command bus signal line 4a according to the value of 0a.

In the above explanation, the I/O decode signal was divided into three blocks, but the number of blocks is arbitrary.
It may be divided for each I/O.

(Effects of the Invention) As described above, the present invention detects an I/O command, activates a plurality of timer circuits by the output of the I/O address decoding circuit, and combines the command status signal output from the CPU with the above-mentioned The output timing of the I/O command is determined based on the values set in multiple timer circuits and the output of the I/O address decoding circuit, and the bus signal line is determined according to the output timing instruction and the value of the command status signal. By outputting I/O commands to the CPU, there is no need to change the firmware even if the performance or speed of the CPU changes, which has the effect of improving economy and reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the I/O command output control method according to the present invention. FIG. 2 is a timing chart showing an example of the operation of the device shown in FIG. 11-13...Timer circuit, 2...Command control circuit, 3...Timer control circuit, 4...Command output circuit, 5...I/O address decoding circuit,
1a, 2a, 3a, 4a, 5a, 10a, 11
a, 12a...signal line.

Claims (1)

[Claims] 1. A method for controlling the output of I/O commands instructing a CPU to read and write to an external device, comprising: a plurality of timer circuits for counting time; and deciphering I/O addresses. an I/O address decoding circuit for activating one of the plurality of timer circuits based on the output of the I/O address decoding circuit; and a command status indicating the type of command output from the CPU. a command control circuit for determining the output timing of the I/O command based on the signal, the values set in the plurality of timer circuits, and the output of the I/O address decoding circuit; and the command status signal and the command. An I/O comprising: a command output circuit for outputting the I/O command to a bus signal line according to instructions from a control circuit;
Command output control method.