JPH056218B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A common control unit including a first microprocessor that commonly controls a plurality of channels, and an individual control unit including an individual microprocessor that individually controls each channel. In the channel processing device,
This is a channel control method that provides activation reservation and activation cancellation means for each channel, making it possible to issue IO commands to different channels continuously.

[Industrial application field]

The present invention provides IO between microprocessors in a channel processing device in a general computer system.
This relates to a method for reserving and canceling instruction activation.

[Prior art and problems]

FIG. 7 is a diagram showing an outline of a general computer system having a channel processing device. In FIG. 7, 1 is a central processing unit, 2 is a main storage device, 3 is a channel processing device, CH is a channel, and IO is an input/output device. Channel processing device 3
receives input/output commands from the central processing unit 1, reads channel command words from the main storage device 2, controls the channel CH according to the channel command words, and performs the functions stored in the main storage device 2. Send the data to the input/output device IO, store the data from the input/output device IO to the main storage device 2, store the status at the end of the data to the main storage device 2, or send the data from the input/output device IO to the main storage device 2. It is used to issue an output end interrupt.

FIG. 8 is a diagram showing an outline of a conventional channel processing device. In FIG. 8, 4 is a storage control device;
Reference numeral 5 indicates a first channel common control section, 6 indicates a second channel common control section, and 7 indicates an individual control section. Parts 5 to 7 are present in the channel processing device 3. The first channel common control unit 5 is responsible for decoding and execution of instructions (for the CPU), load/store of subchannels (for the MCU), and IO interrupts (for the CPU).
CPU), etc. The second common control unit 6 has functions such as analysis and execution of IO commands, loading/store of subchannels, data transfer to and from the main storage device 2, reading of channel command words, and IO interrupts. One individual control unit 7 is provided for each channel, and its main functions are sequence control of the IO interface, and tag-out by checking the on/off of the tag-in signal of the IO interface. Function to turn on/off signals, IO
It has functions such as analyzing the interface. Each of the first channel common control section 5, the second channel common control section 6, and the individual control section 7 includes a microprocessor.

In the prior art, communication between the microprocessor of the first channel common control section 5 and the microprocessor of the individual control section 7 is performed by microcommunication, which takes time. Note that micro-comunication refers to communication using microprograms. For example, if the microprogram of the common control unit 5 is K and the microprograms of each individual channel are C ₁ , C ₂ , ..., _Co ,
When an IO command is issued to C _o , K exchanges signals with C _o under the control of each microprogram. For example, when the first channel common control unit 5 specifies a certain channel and issues an activation reservation,
The individual control unit 7 uses a microprogram to check the channel status, and if it is possible to accept input/output commands,
A response is returned to the first channel common control unit 5 by the microprogram.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a channel control method that enables high-speed communication between a first channel common control section and an individual control section.

[Means to achieve the purpose]

Therefore, the channel control method of the present invention is
In a channel processing device in a computer system, a channel common control unit 5 includes a first microprocessor 14 that commonly controls a plurality of channels.
and an individual control unit 7 including an individual microprocessor 15 that individually controls the processing of each channel in the order of the channel number, and a register element 8 corresponding to each channel,
It has a channel state storage means S1 for storing channel state data in each register element 8, and a register element 9 corresponding to each channel,
IO command issuance storage means S2 that stores IO command issuance data in each register element 9; and channel activation reservation storage means S3 that has register elements 10 corresponding to each channel and stores activation reservation existence data in each register 10. and an instruction code storage means S4 which has a register element 11 corresponding to each channel and stores an instruction code in each register element 11, and the individual control unit 7 stores the channel state in the register element 8 of the channel state storage means S1. The channel common control unit 5 can write the state data and read the channel state data in the register element 8 of the channel state storage means S1, and the channel common control unit 5 can write data in the register element 9 of the IO instruction issue storage means S2. The individual control unit 7 is an IO command issuing storage means S2
The channel common control unit 5 can write activation reservation data and no activation reservation data in the register element 10 of the channel activation reservation storage means S3. 7 can read the data of the register element 10 of the channel activation reservation storage means S3, and the channel common control section 5 can read the data of the register element 10 of the channel activation reservation storage means S3.
An instruction code can be written in the register element 11 of No. 4, and the individual control unit 7 has an instruction code storage means S.
When the individual control unit 7 detects that activation reservation data exists in a certain register element 10 of the channel reservation storage means S3, the individual control unit 7 reads the data of the register element 11 of the channel reservation storage means S3. The channel status data of the corresponding register element 8 of S1 is checked, and if the channel status data indicates that the input/output command can be accepted, the channel common control unit 5 is notified that the input/output command can be accepted, and the channel status data indicates that the input/output command can be accepted. If the input/output command is not accepted, it is configured to notify the channel common control unit 5 of the input/output command acceptance failure, and the channel common control unit 5 confirms the response that the instruction code has been set in the instruction code storage means S4. Sometimes, it is characterized by being configured to be able to start processing for the next channel.

[Embodiments of the invention]

FIG. 1 is a diagram showing an outline of an example of a channel processing device of the present invention. The same reference numerals as in FIG. 8 represent the same parts. Sixteen channels are connected to the individual control unit 7. When the central processing unit 1 issues an input/output command, the first channel common control unit 5 sends an activation reservation to the individual control unit 7, checks the status of the corresponding channel, and then issues the input/output command to the individual control unit 7. send. Upon receiving the input/output command, the individual control unit 7 sends it to the second channel common control unit 6,
Requests input/output instructions, parsing, and execution. In addition, the individual control unit 7 requests the second channel common control unit 6 to perform data transfer, IO interrupt, and other processing. For example, at the 0th timing, the individual control unit 7 reads out and executes a microinstruction for controlling the channel of machine number 0 from the control memory, and at the first timing, controls the microinstruction for controlling the channel of machine number 1. Read it from the memory and execute it. At the F-th timing, read the microinstruction for controlling the channel of machine number F from the control memory and execute it. At the next timing 0, control the channel of machine number 0 from the control memory again. Read and execute the microinstruction for The same applies hereafter.

FIG. 2 is a diagram for explaining communication between the first channel common control section and the individual control sections in the present invention. In FIG. 2, S1 is a channel state storage means, S2 is an instruction issue storage means, S3 is a channel activation reservation storage means, S4 is an instruction code storage means, 8 to 11 are register elements, 12 is an operation code register, 13 is a decoder, 1
4 represents a first microprocessor, and 15 represents an individual microprocessor. The channel state storage means S1 has 16 register elements 8, which are connected in series to form a shift register, and the contents of the register elements 8 are shifted to the right every cycle. Other storage means S2,
The same applies to S3 and S4. Individual control section 7
reads the contents of the leftmost register elements 8 to 11, and the first channel common control unit 5 writes data to the leftmost register elements 9 to 11. The individual control unit 7 writes data to the third register element 8 from the left end. Note that register elements 8 to 10 each consist of one bit, and register element 11 consists of a plurality of bits indicating an instruction code. Writing data means register element 8
This means that ON/OFF is determined for the register elements 10 to 10, and an instruction code is written as data for the register element 11. An operation code is issued from the first channel common control unit 5 in synchronization with the channel number.
It is set in code register 12 and its contents are decoded by decoder 13. According to the decoding result, an ON selection instruction signal is sent to one or more of the leftmost register elements 9 to 11. The leftmost register element for which the selection instruction signal is on takes in the data sent from the first channel common control unit 5, and the leftmost register element for which the selection instruction signal is off takes in the contents of the rightmost register element. take in. For example, when the individual control unit 7 detects that the startup reservation bit for the channel of machine number 0 is turned on, if the state of the channel of machine number 00 is such that input/output commands can be accepted, the individual control unit 7 sends the command to the first common control unit 5. A response to that effect is returned.

Figure 3 shows the first channel when the subchannel is busy.
FIG. 3 is a diagram showing operations of a channel common control unit and an individual control unit. Now, central processing unit 1 is START
Assuming that the IO FAST RELEASE command has been issued, the first channel common control unit 5 makes a startup reservation for the specified channel (for example, machine number 0), and at the same time updates the main storage 2 to the corresponding subchannel ( (specified by an input/output instruction). When the activation reservation is detected, the individual microprocessor 15 responds to the first common control unit 5 to that effect if the channel of machine number 0 is in a state where it can accept input/output commands. If the command cannot be accepted, a response to that effect will be given. If the subchannel read from the main storage device 2 indicates busy, the first channel common control unit 5 writes logic "0" to the channel activation reservation storage means S3 at the timing determined by the channel with machine number 0. This logic "0" means cancellation of the activation reservation.

FIG. 4 is a diagram showing the operations of the first channel common control section and the individual control section when the subchannel is usable and the channel is idle. When it is determined that the individual control unit is capable of accepting input/output commands and that the corresponding subchannel is usable, the first channel common control unit 5 issues an IO command at a timing determined by the channel with machine number 0. S2
A logic "1" is set in the input/output command, and at the same time, an input/output command is set in the instruction code storage means S4. Note that the microprogram of the individual control section 7 has the status display set in advance. First channel common control unit 5
After confirming the response that the instruction code has been set in the instruction code storage means S4, processing for the next channel can be started. When the individual control section 7 finds that the input/output command for the channel of machine number 0 has been set, it requests the second channel common control section 6 to analyze and execute the input/output command.

FIG. 5 is a diagram showing the microflow of the individual control unit when the channel is idle.

It is checked whether or not the activation reservation state is set, and if it is off, the process is performed, and if it is on, the process is performed.

Whether there is an IO request (e.g. REQUEST
Check whether the IN signal is on or not. If No, return to the process in step 2, and if Yes, perform the process in step.

Performs IO processing.

Check whether an IO instruction is being executed or not. If it is on, perform the process; if it is off, perform the process.

Execute IO instructions.

It is checked whether or not the activation reservation state is set, and if it is on, the process returns to step 2, and if it is off, the process returns to step .
Returning to the process means cancellation of the activation reservation.

FIG. 6 is a diagram showing the microflow of the individual control unit when the channel is busy.

It is checked whether or not the activation reservation state is set, and if it is off, the process is performed, and if it is on, the process is performed.

Check whether IO has finished. If the answer is No, return to the process in step 2. If the answer is yes, proceed to the process in step 3.

Performs IO termination processing.

Check whether an IO instruction is being executed or not. If it is on, perform the process; if it is off, perform the process.

Execute IO instructions.

It is checked whether or not the activation reservation state is set, and if it is on, the process returns to step 2, and if it is off, the process returns to step .
Returning to the process means cancellation of the activation reservation.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a channel status display storage means, an IO command issue storage means, a channel activation reservation storage means, and a channel activation reservation storage means are provided between the first channel common control section and the individual control section. Since the code storage means is provided for each channel, it is possible to easily make and cancel activation reservations, and it is also possible to issue IO commands to different channels continuously.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an overview of an example of a channel processing device of the present invention, FIG. 3 is a diagram showing the operation of the first channel common control unit and the individual control unit when the subchannel is busy, and FIG. 4 is a diagram showing the operation of the first channel common control unit and the individual control unit when the subchannel is usable and the channel is idle. A diagram showing the operation of the individual control unit,
Fig. 5 is a diagram showing the microflow of the individual control unit when the channel is idle, Fig. 6 is a diagram showing the microflow of the individual control unit when the channel is busy, and Fig. 7 is a diagram showing the microflow of the individual control unit when the channel is busy. FIG. 8 is a diagram showing an overview of a conventional channel processing device. 1...Central processing unit, 2...Main storage device, 3...
...Channel processing device, 4...Storage control device, 5...
...First channel common control section, 6...Second channel common control section, 7...Individual control section, 8 to 1
1...Register element, 12...Operation
code register, 13... decoder, 14... first microprocessor, 15... individual microprocessor, S1... channel state storage means, S
2...IO command issue storage means, S3...channel activation reservation storage means, S4...instruction code storage means.

Claims (1)

[Claims] 1. In a channel processing device in a computer system, a channel common control section 5 including a first microprocessor 14 that commonly controls a plurality of channels.
and an individual control unit 7 including an individual microprocessor 15 that individually controls the processing of each channel in the order of the channel number, and a register element 8 corresponding to each channel,
It has a channel state storage means S1 for storing channel state data in each register element 8, and a register element 9 corresponding to each channel,
IO command issuance storage means S2 that stores IO command issuance data in each register element 9; and channel activation reservation storage means S3 that has register elements 10 corresponding to each channel and stores activation reservation existence data in each register 10. and an instruction code storage means S4 which has a register element 11 corresponding to each channel and stores an instruction code in each register element 11, and the individual control unit 7 stores the channel state in the register element 8 of the channel state storage means S1. The channel common control unit 5 can write the state data and read the channel state data in the register element 8 of the channel state storage means S1, and the channel common control unit 5 can write data in the register element 9 of the IO instruction issue storage means S2. The individual control unit 7 is an IO command issuing storage means S2
The channel common control unit 5 can write activation reservation data and no activation reservation data in the register element 10 of the channel activation reservation storage means S3, and the channel common control unit 5 can write data with activation reservation and no activation reservation data. 7 can read the data of the register element 10 of the channel activation reservation storage means S3, and the channel common control section 5 can read the data of the register element 10 of the channel activation reservation storage means S3.
An instruction code can be written in the register element 11 of No. 4, and the individual control unit 7 has an instruction code storage means S.
When the individual control unit 7 detects that activation reservation data exists in a certain register element 10 of the channel reservation storage means S3, the individual control unit 7 reads the data of the register element 11 of the channel reservation storage means S3. The channel status data of the corresponding register element 8 of S1 is checked, and if the channel status data indicates that the input/output command can be accepted, the channel common control unit 5 is notified that the input/output command can be accepted, and the channel status data indicates that the input/output command can be accepted. If the input/output command is not accepted, the channel common control unit 5 is configured to be notified of the input/output command acceptance failure, and the channel common control unit 5 confirms the response indicating that the instruction code has been set in the instruction code storage means S4. A channel control method, in some cases, being configured to start processing for the next channel.