JPS5914775B2 - Common memory lock method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common memory locking scheme in multiprocessor systems.

Multiprocessor systems mainly consist of multiple CPUs (
A central processing unit) and a common memory that serves as a data exchange medium between these CPUs, and the common memory is occupied by the plurality of CPUs in a time-sharing manner, and necessary data is read or written. Ru.

In this case, access to the common memory is
Since there should be no contention by the PU, a common memory locking means is required to prevent such contention. Conventionally, the following two methods have been put into practical use as methods for realizing this common memory locking means. First, in the first method, one CPU of the multiprocessors is provided with a monitoring function for monitoring a specific area on the common memory, and if multiple CPUs attempt to access this specific area, the This is a method in which a CPU having a monitoring function performs control to resolve the conflict. The second method is for each CP
In this method, U is provided with the above-mentioned monitoring function, and each CPU uses its own monitoring function to determine whether access is possible before accessing the common memory, thereby preventing contention. In this method, it is necessary to prepare a privileged instruction called TestandSet in each CPU, and to provide a function in the main memory to complete reading and writing within one memory cycle. However, the first and second methods have the following drawbacks or problems.

In the first method, the hardware is simple, but since one CPU (master CPU) controls the entire system, privileged instructions must be distinguished so that they can only be used by the master CPU, and privileged instructions must be distinguished so that only the master CPU can use them. The input signals must also be concentrated only on the master CPU. Furthermore, each C
Since the communication sequence between PUs becomes complicated and takes time, it becomes difficult to configure the LoadShare system. In addition, when a failure occurs in the master CPU, switching to another CPU becomes complicated, leading to a decrease in reliability. In any case, the first method is a complicated method of operation. On the other hand, in the second method, although there is no need to switch to another CPU as mentioned above, the hardware is complicated, and especially in small-scale multiprocessor systems, the burden on the hardware is large and the cost is high. cause an increase. For example, in order to prepare TestandSet, we need to add the instruction function to the CPU, add the function to read and write to the main memory within one memory cycle, and then add the function to read and write to the main memory within one memory cycle. It is necessary to add an interface in between to notify that it is a TestandSet command. In any case, the second method complicates the hardware. Therefore, the present invention has the advantage that it is possible to eliminate the drawbacks or problems of the first method and the second method described above, and that the operation is simple and the hardware can remain the same as before. The purpose of this paper is to propose a common memory locking method.

In accordance with the above object, the present invention allows one CPU requesting access to the common memory to first access a specific area within the common memory.
A specific pattern indicating the idle state of the common memory area is read, and by reading this specific pattern, it is detected that it can be accessed, and a code unique to the own CPU is written in the specific area, and the unique code is written again. This is characterized in that the common memory area is accessed by one CPU only after it has been read and confirmed that there has been no change.

According to this method, although the operation of re-reading the unique code is added, the other operations are completely normal operations. It is clear that there is no need to read out the specific pattern to the area and write to change the specific pattern to a pattern that indicates a busy state, and the hardware can remain the same as before. The present invention will be explained below with reference to the drawings. 1st
The figure is a block diagram illustrating a general multiprocessor system.
Each CPU is provided with a main memory device (MM,) 12-1 and a main memory device (MM2) 12-2, respectively.

Now, the information given by CPUll-1 is sent to CPU2ll.
-2 is used to perform the following processing, then CP
Before Ull-1 writes all the information to the common memory (CM) 13 or processes it, the CPU 2l
If l-2 were to access the common memory l-3, it is clear that normal data exchange would no longer be possible. Therefore, a common memory locking scheme is required to prevent the common memory from being destroyed due to logical access conflicts. FIG. 2 is a block diagram illustrating a general method for implementing the common melody lock system.

In this figure, the same reference numerals as in FIG. 1 indicate the same components. The common memory 13 has a specific area 21 therein, and before accessing the common memory area 22 in the common memory 13, the CPU ll-1 and the CPU 2ll-2 first access the specific area 21.
The data is read (Read in the figure). In the conventional example, ``1'' or 601 is written in the specific area 21, and if the common memory area 22 is accessed by one CPU, the value is ``11'', and if it is not accessed, the value is ``60''. When a program in the CPU of the processor system uses the common memory area 22, it transfers control to the hardware by issuing a privileged instruction (for example, the above-mentioned TestandSet instruction) and monitors the usage status of the common memory area 22. If this is shown in a flowchart, it will look like Figure 3. First, an access request is issued ("Start" in the diagram), and at this time, a specific area 2
If the content of 1 (FIG. 2) is ``0'' (see the right column of FIG. 3), the privileged instruction proceeds. 6 start 1 if not 601
Return to

At this time, the content of the specific area 21 is rewritten to "1°" (see Write in Figure 2 and the right column in Figure 3).
. Here, access to the common memory area 22 (FIG. 2) by other CPUs is prohibited at all, and a CPU that has obtained a privileged instruction, for example CPUll-1 (FIG. 2), is prohibited from using the common memory area 22. (Refer to ``Access'' in Figure 2 and ``6 Use of common memory area'' in Figure 3.) After use, the contents of the specific area are set to ``01'' again (Refer to ``Write'' in Figure 2 and ``Clear specific area'' in Figure 3). ”), the access is terminated. The above-mentioned method has the drawbacks or problems mentioned above. Therefore, the present invention executes the access based on the flowchart shown in FIG.

In this figure, for example, the CPU, ll-1, which requests the use of the common memory area 22 (FIG. 2), first reads the specific area 21 (FIG. 2) ("Read" in FIG. 4).
). By reading it, it is determined whether the specific area 21 is "0" (6 specific area "0" in FIG. 4).
. When the specific area 21 is “0”, the code specific to CPU1ll-1, for example, CPU1ll-1, continues in the next memory cycle.
The error is written in the specific area 21 ("Write CPU error" in FIG. 4). Furthermore, after a certain timing (6 constant timing 1 in Figure 4), the specific area 21 is read again and it is confirmed whether or not the CPU waterfall has changed (CPU waterfall no change 2 in Figure 4).゛). After checking,
Uses the common memory area 22 and stores it in the specific area 21 after use.
Clear the contents to "01" and end the access. If CPUf) has changed in this check, wait (6 "Wait" in Figure 4) and repeat the same sequence from readout again. . This is already mentioned, "specific area = 60"? The same applies when the specific area becomes \"O" in step 1. In the flowchart of FIG. 4, the reason why the step ``constant timing 1'' is necessary is as follows.

Since the method of the present invention is executed by normal hardware and normal operation,
Reading and writing to (Fig.) is not completed within one memory cycle. As a result, even if the CPU ll-1 intends to write its own CPU name in the specific area 21, if the CPU 2ll-2 reads out the specific area 21 at a timing earlier than the writing, the CPU 2ll-1 will not be able to write the specific area 21 at this point. CPU1ll-1 CPU/1 for specific area 21
6 is not written, and the CPU 2ll-2 reads "O" from the specific area 21. Therefore, the CPU 2ll-2 reads "O" from the specific area 21.
2ll-2 writes its own CPU memory and uses the common memory area 22 (FIG. 2). In this case, CPUll-
1 is the specific area 2 regardless of the operation of CPU2ll-2.
1, but it is eventually erased by the CPU of CPU 2ll-2, which issued an access request later.

Therefore, when such write erase occurs, CPUll-1 is prohibited from using the common memory area 22, so it checks at certain timing whether or not its own CPU has been erased, that is, CPU corruption. You need to check again to see if any changes have been made. This is the reason why "constant timing" is provided, and an example of this is shown in the time chart of Fig. Column C
Write PUl). Now, if the CPU 2ll-2 performs reading at time T2, which is before time T3, the content of the specific area at that point is still "O"("0" in the upper column of this figure). CPU2ll-2 writes its own CPU data (CPU2) at time T4. Therefore, the CPU cascade (CPUl) will be erased by the CPU cassette (CPU2). Therefore, after time T4, use of the common memory area 22 by CPUll-1 is prohibited. When such a situation occurs, CP
Since Ull-1 must yield its use to CPU 2ll-2, the specific area 21 is read out again after a certain timing T to check for CPU corruption. Of course,
If there is no such interrupt from CPU2ll-2, the CPU
Ull-1 will continue to use the common memory area 22. As explained above, according to the system of the present invention, a common memory lock function equivalent to the conventional one can be realized without requiring any special operation or special hardware.

[Brief explanation of the drawing]

Figure 1 is a block diagram illustrating a general multiprocessor system, Figure 2 is a block diagram illustrating a general method for realizing a common memory lock system, and Figure 3 is a block diagram illustrating a general method for implementing a common memory lock system.
The figure is a flowchart showing the process of the conventional method, Figure 4 is a flowchart showing the process of the method of the present invention, and Figure 5 is a flowchart showing the process of the method of the present invention.
The figure is a time chart explaining the reason for the existence of six constant timings in the system of the present invention. In the figure, 11-1 and 11-2 are CPUll3 common memories, 21 is a specific area, and 22 is a common memory area.

Claims (1)

[Claims] 1 It has a plurality of central processing units and a common memory shared by the plurality of central processing units, and before the central processing units use a common memory area in the common memory, A common memory lock method reads a specific area in a memory and makes the common memory area usable when the content of the specific area is a predetermined specific pattern indicating that the common memory area can be used, When the central processing unit 1 reads the specific area and the content of the specific area is the specific pattern,
Subsequently, a code unique to the central processing unit of the first concerned is written to the specific area, and after a certain period of time has elapsed, the specific area is read, and after confirming that there is no change in the contents, the central processing unit of the first concerned writes the code to the common memory. A common memory locking method that uses areas.