JPH056375B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital-to-analog converter (hereinafter referred to as a DA converter), particularly a semiconductor integrated circuit in which resistors with resistance values R and 2R are connected in a ladder shape. consists of
Regarding DA converters.

[Conventional technology]

A circuit diagram of a conventional DA converter of this type is illustrated in FIG.

In FIG. 4, a 4-bit DA converter 11
is seven resistors R1 to R7, four constant current sources _I0
~ _I3 and four switches _S0 ~ _S3 , and the switches _S0 ~ _S3 are turned on and off depending on the values of the input signals _D0 ~ _D3 of the DA converter 11, respectively.
These switches S ₀ to _{S 3} have an input signal of “1”.
It is assumed that the signal is turned on when the signal is at "high level" and turned off when it is "0" (low level).

Low resistance values of resistors R1 to R7 and constant current source I ₀ to
The current value of I ₃ has the following relationship.

R = R2 = R4 = R6 = R R3 = R5 = R7 = 2R I ₀ = I ₁ = I ₂ = I ₃ = I The voltage drop caused by the constant current source I ₀ at the output terminal V _put is ΔV (D ₀ ). Then, ΔV (D ₀ ) = R7 × D ₀ × IR1/R1 + [R2 + R3 {R4 + R5
(R6+R7)}] R3/R3+{R4+R5(R6+R7)}×R5/R5+(R6+
R7) = 1/8RD ₀ I Similarly, constant current sources I ₁ , I ₂ , I ₃ output terminals.
The voltage drop occurring at V _put is expressed as ΔV (D ₁ ) and ΔV, respectively.
(D ₂ ), ΔV(D ₃ ), ΔV(D ₁ )=R7×D ₁ ×I×R3(R1+R2)/R3(R1+R2)+R4+{R5(R6+
R7)} ×R5R5+(R6+R7) = 1/4RD ₁ I ΔV(D ₂ )=R7×D ₂ ×I ×R5{R4+R3(R1+R2)}/R5{R4+R3(R1+
R2)}+(R6+R7) =1/2RD ₂ I ΔV( _D3 )=R7×D ₃ ×I ×R6+[R5{R4+R3(R1+R2)}]/R6+[R5{
R4+R3(R1+R2)}+R7= _RD3I However, RR' represents the parallel resistance value of R and R'.

As a result, the output voltage V of this DA converter 11 becomes as shown in the equation.

V = E4 (ΔV (D ₀ ) + ΔV (D ₁ ) + ΔV (D ₂ ) + ΔV
( _D3 )) =E4-R( _D3 +1/ _2D2 +1/ _4D1 +1/ _8D0 )I... However, E4 is the voltage value of the power source E4.

Therefore, it can be seen that the output voltage V is the DA conversion output of the input signals (D ₃ , D ₂ , D ₁ , D ₀ ) with D ₃ as the most significant bit.

[Problem that the invention seeks to solve]

The operation of the conventional DA converter described above can be tested by measuring the output voltage V for all patterns of digital input signals D ₀ to _{D 3} . However, since it does not have a dedicated terminal for measurement, the output terminal is also used when measuring the output voltage V, but if multiple DA converters like this are used,
In the case of (N) semiconductor integrated circuits, it is necessary to connect the output terminal V _put to the measuring device N times, which is a disadvantage.

In addition, it has become possible due to recent rapid progress in integrated circuit technology, and it has become possible to
Even when a DA converter and a controlled circuit controlled by the DA converter are integrated, the output terminal of the DA converter may be used as a test terminal to connect to a pin of the integrated circuit for the sole purpose of testing the operation of the converter. There must be. Therefore, when a large number of DA converters and their controlled circuits are integrated into one chip, the number of pins must be increased by the number of DA converters and their controlled circuits.
The disadvantage is that the number of pins on the integrated circuit increases.

The DA converter of the present invention requires only one connection between the output terminal and the measuring instrument during testing;
Even when a large number of DA converters and their controlled circuits are integrated into one chip, the device has the feature that the operation of all of these DA converters can be tested with a single test terminal.

[Means for solving problems]

The DA converter of the present invention is a digital-to-analog converter configured by connecting a plurality of first resistors and a plurality of second resistors each having a resistance value twice that of the first resistor in a ladder shape. The other end of the second resistor, one end of which is connected to the output terminal of the digital-to-analog converter, is separated from the other resistors, and the other end is separated from the first bias supply source that supplies a bias voltage. It is characterized by having a second bias supply source that supplies a bias voltage of the same value as the bias voltage to a common connection point of the resistor group.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of a first embodiment of the present invention, in which a DA converter 3, a controlled circuit 5,
A first bias supply source 1 and a second bias supply source 2 are housed. Therefore, the output terminal V ₀₀ and the bias terminals B ₁ and B ₂ do not need to be external terminals.

Although the other end of the resistor 7, which is not the output terminal V ₀₀ side, is separated from the resistor R5, the DA converter 3 is configured so that the bias terminals B1 and B2 are at the same potential as described later. Therefore, it has the same configuration as the DA converter 11 shown in FIG.

One ends of the resistors R1, R3 and R5 of the DA converter 3 are commonly connected to the bias terminal B1 which is the output terminal of the second bias supply source 2, and one end of the resistor R7 is connected to the bias terminal B1 which is the output terminal of the second bias supply source 1. It is connected to bias terminal B2 which is an output terminal.

The second bias supply source 2 is composed of an amplifier 7, a transistor Q1, and a constant current source 9. Since the amplifier 7 and the transistor Q1 form a voltage follower circuit, the potential of the bias terminal B1 is the + side input of the amplifier 7. The constant current source 9, which has a potential equal to the potential of the power source E2 applied to the DA converter 3, is a constant current source necessary to keep the transistor Q1 on whose current flowing into the DA converter 3 is zero.

The first bias supply source 1 and the second bias supply source 2
The circuit configuration is the same as that of the bias terminal B2, and the potential of the bias terminal B2 is equal to the potential of the power supply E2.

The collector of the transistor Q2 of the first bias supply source 1 is connected to a measurement terminal T, and an ammeter 6 is connected between this terminal T and the power supply terminal _Vcc .

As a result of the above configuration, the DA converter 3
It operates in the same way as the DA converter 11 shown in the figure. The voltage of output terminal V ₀₀ of DA converter 3 is set to V ₀
Then, if the input impedance of the controlled circuit 5 is sufficiently large, the output voltage V ₀ will be the same as that of the DA converter 11.
It becomes equal to the output voltage V of . If the input impedance of the controlled circuit 5 is not large enough, the output voltage V ₀ will not be equal to the output voltage V, but the output voltage V ₀ will be equal to the pattern of the input signals D ₀ to D ₃ (D ₀ ,
It is clear that the output is the DA conversion output of D ₁ , D ₂ , D ₃ ).

Since the bias terminal B2 has a constant potential equal to the potential of the power source E2, a current corresponding to the output voltage _V0 flows through the resistor R7 having a resistance value of 2R connected to the output terminal _V00 . In other words, when the input signal (D ₀ to _{D 3} pattern is (0, 0, 0, 0), the minimum current flows, (1, 0, 0, 0), (0, 1, 0, 0) When the input signal is increased in this order, the current increases in constant steps, and the maximum current flows at (1, 1, 1, 1).Therefore, the operation of the DA converter 3 can be tested using the input signal pattern (D ₀ , D ₁ , D ₂ , D ₃ ), for example, from (0, 0, 0, 0) to (1, 1, 1, 1), and measure the change in the current flowing through resistor R7 with an ammeter. This can be done by

Note that the input impedance of the amplifier 8 is usually sufficiently large so that the base current of the transistor Q2 can be ignored, and because of the presence of the constant current source 10, the change in the collector current of the transistor Q2 is caused by the current of the resistor R7. almost equal to the change in

FIG. 2 shows a second embodiment of the invention. This embodiment shows that the operation of two R-2R ladder type DA converters 3 and 13, which share a common bias supply source, can be tested using the measurement terminal T1 pin. The configuration of this embodiment is as follows.

4-bit R-2R ladder type DA converter 3,3
A bit R-2R ladder type DA converter 13, two controlled circuits 5 and 15, a first bias supply source 1 and a second bias supply source 2 are housed in one chip.

The DA converter 13 has the same configuration as the DA converter 3, although the number of bits of the input signal is different. That is,
One end of the resistor R12 of the DA converter 13 is connected to the output terminal of the first bias supply source 1, and one end of the resistor R12 is connected to the output terminal of the first bias supply source 1.
10 are both connected to the output of the second bias supply source 2.

Therefore, one end of the resistor R7 of the DA converter 3 and one end of the resistor R12 of the DA converter 13 are both connected to the output terminal of the first bias supply source 1.

The first bias supply source 1 and the second bias supply source 2 are the same circuits as those shown in FIG. 1, and make the output voltage equal to the voltage of the power supply E2. The collector of the transistor Q2 of the first bias supply source 1 is connected to the measurement terminal T and to a resistor R20 whose other end is connected to the power supply terminal _Vcc .

In this embodiment, two DA converters 3 and 1
For example, test 3 may be performed as follows.

First, the operation of the DA converter 3 will be tested. For this purpose, the input signal pattern (D ₄ , D ₅ , D ₆ ) of the DA converter 13 is fixed to, for example, (0, 0, 0). At this time, the switch of DA converter 13
Since S ₄ , S ₅ , and S ₆ are turned off, if the voltage at the output terminal V ₀₄ of the DA converter 13 is V ₁ , the output voltage V ₁ is fixed at the highest potential and is
The current flowing into the DA converter 13 becomes constant.

Under these conditions, the input signal pattern (D ₀ , D ₁ , D ₂ , D ₃ ) of the DA converter 3 was changed in order from (0, 0, 0, 0) to (1, 1, 1, 1). The test is performed by measuring the change in the collector current of the transistor Q2 of the first bias supply source 1 at that time.

As means for detecting the collector current of the transistor Q2, this embodiment includes a resistor R20 and a voltmeter 25 in place of the ammeter 6 shown in FIG. Connect one end of resistor R20 to the power supply terminal _Vcc of the integrated circuit,
The other end is the collector of transistor Q2 and the measurement terminal T.
, the change in the collector current of the transistor Q2 is converted into a change in the voltage across the resistor R20, which can be measured by connecting the voltmeter 25 between the power supply terminal _Vcc and the measurement terminal T. In this case, if the resistor R20 is built into the integrated circuit, there is an advantage that the measurement terminal T can be left open except during testing.

Next, the operation of the DA converter 13 can be tested in the same way. That is, first, DA converter 3
For example, if the input signal pattern (D ₀ , D ₁ , D ₂ , D ₃ ) of DA
Input signal pattern of converter 13 (D ₄ , D ₅ , D ₆ )
What is necessary is to change the current from (0, 0, 0) to (1, 1, 1) and measure the change in the collector current of the transistor Q2 at that time in the same way.

In this example, two bias supply sources are used in common.
Although this is a case in which the DA converters are housed in one chip, it is clear that the same can be done in the case of three or more DA converters connected to the same bias supply source.
In this way, testing of the operation of a type DA converter can be performed at one pin of the measurement terminal without the need for a large number of R-2Rs with a common bias supply source.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. This example uses two different bias voltages.
This shows that the operation of the DA converters 3 and 18 can be tested using the test terminal pin 1.

The configuration of this embodiment is as follows.

The output terminal _V00 of the 4-bit R-2R ladder type DA converter 3 is connected to the controlled circuit 5. The DA converter 3 is shown in FIGS. 1 and 2.
It is the same as the DA converter 3, and one ends of resistors R1, R3 and R5 are commonly connected to the output terminal of the second bias supply source 2, and one end of the resistor R7 is connected to the output terminal of the first bias supply source 1. connected to the terminal. The first and second bias supply sources 1 and 2 are also the same as the bias supply sources 1 and 2 in FIGS. 1 and 2,
Make the output terminal equal to the voltage of the power source E2.

Further, the bit DA converter 18 has the same configuration as the DA converter 3, and one ends of the resistors R13, R15 and R17 are connected in common to the output terminal of the second bias supply source 17, and one ends of the resistors R19 and R17 are connected in common to the output terminal of the second bias supply source 17. One end of the bias voltage source 16 is connected to the output terminal of the first bias supply source 16 . First and second bias supply sources 16, 17
Both have the same circuit configuration as the first and second bias supply sources 1 and 2, and make the output voltage equal to the voltage of the power supply E3.

The collector of the transistor Q2 of the first bias supply source 1 and the collector of the transistor Q4 of the first bias supply source 16 are commonly connected, and the other end is a power supply terminal.
Resistor R20 is connected to V _cc and measurement terminal T is connected.

The operation of the two DA converters in this embodiment is tested as follows.

First, the input signal pattern (D ₇ , D ₈ , D ₉ , D ₁₀ ) of the DA converter 18 is changed to (0, 0, 0,
0). At this time, the collector current of the transistor Q3 of the second bias supply source 17 becomes a constant current, and the voltage across the resistor R20 does not change due to this current. Then, the input signal pattern (D ₀ , D ₁ , D ₂ , D ₃ ) of the DA converter 3 is changed to (0,
0, 0, 0) to (1, 1, 1, 1) in order, and the change in the collector current of the transistor Q2 of the first bias supply source 1 at that time is similar to the example shown in FIG. The operation of the DA converter 3 is tested by measuring the voltage across the resistor R20.

Next, the input signal pattern of the DA converter 3 (D ₀ ,
D ₁ , D ₂ , D ₃ ) are fixed to (0, 0, 0, 0), and the input signal pattern (D ₇ , D ₈ , D ₉ , D ₁₀ ) of the DA converter 18 is fixed to (0, 0, 0, 0). The operation of the DA converter 18 is tested by changing the voltage from 0, 0, 0) to (1, 1, 1, 1) in order and measuring the change in voltage across the resistor R20 at that time.

In this embodiment, two sets of bias supply sources 1, 2 and 1 are used.
6 and 17 each have one R-2R ladder type
Only DA converters 3 and 18 are connected, but even if a large number of R-2R ladder type DA converters are connected to each bias supply source as shown in Figure 2, the measurement terminal T1 pin will be connected in the same way. It is clear that the operation of all DA converters can be tested.

Furthermore, in this embodiment, there are two sets of bias supply sources, but even if there is an R-2R ladder type DA converter connected to more sets of bias supply sources, all the bias supply sources can be connected to the measurement terminal T1 pin. It is also clear that the operation of the DA converter can be tested.

〔Effect of the invention〕

As explained above, the present invention provides a resistance value connected to an output terminal of an R-2R ladder type DA transformer.
By isolating the bias supply source for a 2R resistor and detecting the change in current flowing through that resistor,
This has the advantage that the operation of a large number of R-2R ladder-type DA converters can be tested by simply providing one pin for measurement.

[Brief explanation of the drawing]

1, 2, and 3 show the first, second, and third embodiments of the present invention, and FIG. 4 shows a conventional example. 1, 16...first bias supply source, 2, 17...
...Second bias supply source, 3, 11, 13, 18...
...DA converter, 5, 15, 20...controlled circuit,
6... Ammeter, 7, 8, 21, 22... Amplifier,
9, 10, 23, 24, I ₀ ~ I ₁₀ ... constant current source, 2
5...Voltmeter, R1~R20...Resistor, S0 _~
S ₁₀ ... Switch, D ₀ ~ _{D 10} ... Input signal, Q1
~Q4...Tomunjista, V ₀₀ , V ₂₁ , V ₀₂ , V _put
...Output terminal, B1, B2...Bias terminal,
V _cc ...Power supply terminal, T...Measurement terminal, E1 to E4
……power supply.

Claims (1)

[Claims] 1. A digital-to-analog converter configured by connecting a plurality of first resistors and a plurality of second resistors each having a resistance value twice that of the first resistor in a ladder shape, comprising: a first bias supply source that separates the other end of the second resistor, one end of which is connected to the output terminal of the digital-to-analog converter, from other resistors and supplies a bias voltage to the other end; a second supplying a bias voltage having the same value as the bias voltage to a common connection point of the resistor group;
A digital-to-analog converter comprising a bias supply source.