JPH0568667B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the configuration of a wave receiving phaser for an electronic scanning ultrasonic tomography apparatus.

[Background of the invention]

The configuration of a conventional receiving phaser will be explained below using the drawings. FIG. 1 represents a trapezoidal field of view of an ultrasonic tomography device. In the figure, sections (1) and (2) are linear sections,
(3)-(4)-(5) are the slopes of deflection angle θ, (6) are the deflection angle −θ
represents one scanning line of the slope of .

In order to deflect the ultrasonic beam as shown in the figure, it is necessary to control the phase of the transmitted and received signals of each array element. FIG. 2a is a diagram showing a circuit configuration for phasing a received signal from the direction of deflection angle θ.
1, 2, 3, ..., N are array elements, S ₁ to _{S N} are sample and hold circuits (hereinafter abbreviated as S/N circuits),
11-1 is an adder, and 12-1 is an output terminal.
C ₁ -C _N and _CA are control signals. AA' is the receiving phase plane with the deflection angle θ, and in order to perform phase delay and addition of the input signals of the square array elements with the same phase, the input signal of the i-th element is delayed by (N-i)τ. rear,
It is necessary to add the signals of all elements. Here, τ
is the delay time between one element and is given by the following equation.

τ=d _sio θ/v (1) Here, θ is the deflection angle, d is the element spacing, and v is the speed of sound.

In order to realize the signal delay as described above, the control signal shown in FIG. 2b may be applied to the S/H circuits S ₁ to S _N of each array element. That is, the control signal
C ₁ is the same as the timing of the received pulse, and _the control signals C ₂ to C _N and C _A are each τ
~(N-1) τ and τ _A are delayed. However, τ _A
>(N-1)τ. The received signals input to each element 1 to N are held by the S/H circuits S ₁ to S _N at the timing of the control signals C ₁ to C _N , respectively, and added by the adder 11-1 at the timing of C _A. Ru.

In the conventional receiving phaser configured as described above, the hold time (delay time) of the S/H circuit S _i of the i-th element is (N-i)τ, and the maximum hold time (N-1 ) τ must be less than or equal to the sampling period T. Therefore, the inter-element delay is τ<T/N-1 (2), that is, the deflection angle θ is limited by the following equation.

θ<sin ^-1 vT/d(N-1) (3) Since the sampling period T is determined by the ultrasonic frequency, the deflection angle θ is limited by the number of array elements N. If N is large, θ It needs to be made smaller. Therefore, it has been difficult to obtain a large trapezoidal field of view as shown in FIG. 1 with the conventional receiving phaser.

Furthermore, as a method for achieving a delay time longer than the sampling period T, there is also a method shown in FIG. 3a. The figure shows a configuration in which the number of array elements is four for the sake of simplicity. For array elements 1 to 4, S/H circuits S ₁ to _{S 4} and adders 11-1 to 11-
3 are alternately arranged in series, the other inputs of the adders are connected to the elements, and the S/H outputs of each element are sequentially added in series to perform phasing. Figure 3b shows the S/H circuit S ₁
It shows the control signal of ~S ₄ , respectively C ₁ ~
It is held at the timing of C ₄ . The received signal of element 1 is sampled and held by the S/H circuit _S1 at the timing of C1, and the received signal is sampled and held at the timing of C1 by the S/H circuit _S1 , and then the received signal is sampled and held by the S/H circuit S1 at the timing of _C2 , which is delayed by the inter-element delay τ.
The result of addition with the received signal of element 2 is sampled and held in the S/H circuit _S2 at the timing of . Similarly, after delaying by τ again in S/H circuit _S2 ,
It is added to the received signal of element 3, sampled and held in the S/H circuit _S3 at the timing of _C3 , delayed again by τ, and added to the received signal of element 4, and then sampled and held in the S/H circuit S3 at the timing of _C3 . The signal is sampled and held in the /H circuit _S4 , and the result of addition of the in-phase signals of each element is output to the output terminal 12-1. In this method, the delay time 3τ of the signal of element 1 relative to the signal received by element 4 can be made longer than the sampling period T.

However, even if the above method is used, sampling cannot be performed at a period shorter than the delay time τ between elements. That is, the deflection angle θ is limited by the following equation.

θ=sin ^-1 vT/d (4) Also, as the ultrasonic frequency increases, it is necessary to shorten the sampling period T according to the sampling theorem. is limited. Therefore, even when the frequency is increased, it is difficult to obtain a large trapezoidal field of view as shown in FIG.

[Purpose of the invention]

The present invention was made to solve the problems of the conventional receiving phaser, and it is possible to obtain a large trapezoidal field of view even when the number of array elements is large or the frequency of the ultrasonic wave used is high. The purpose of the present invention is to provide a receiving phaser for an ultrasonic tomography device that can perform the following steps.

[Summary of the invention]

The feature of the present invention is that the phasing delay for each array element is configured by an S/H circuit, and the S/H circuit and changeover switch for each element are provided in multiple layers, and the received signal from one element is By time-divisionally sample-holding in the S/H circuit, the sampling rate of one S/H circuit is reduced, and phasing with a delay time longer than the sampling period of the received signal is realized. The aim is to obtain a large deflection angle for sound waves.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 4a is a diagram showing the configuration of a parallel multilayer receiving phaser according to the present invention. Here, to simplify the explanation, we will explain the received signals of four elements by three layers of S/H.
A case where phasing is performed using a circuit will be explained. 1 to 4 are array elements, _S11 to _S14 , _S21 to _S24 , _S31 to _S34 , _S10 to
S ₃₀ is S/H circuit, W ₁ to W ₆ are switches, 11-
1 is an adder, and 12-1 is an output terminal. Figure 4b shows the S/H circuits S ₁₁ to _{S 34} , S ₁₀ to _{S 30} and the switches.
This shows the control signals of W ₁ to W ₆ , respectively.
Sample and hold is performed at timings C ₁₁ to _{C 34} and C ₁₀ to C ₃₀ , and the switch is turned on at timings CW ₁ to CW ₆ .

If the delay time between each element is τ, the delay time of element 1 with respect to element 4 is 3τ, and the S/
The hold time C ₁₄ of the H circuit S ₁₄ is delayed by 3τ with respect to the hold time C ₁₁ of S ₁₁ . After the signal of element 4 is held at the timing of _C14 , the switch _W1 is turned on after a delay of settling time Δτ, and at the same time, the hold signals of S11 to S14 are added by the adder 11-1, and the hold signals of _S11 to _S14 are added to the signal of _C10. It is held at S ₁₀ at timing. At the timing of CW ₄ , which is delayed by the settling time Δτ from C ₁₀ , the switch W ₄ is turned on (high level is in the ON state), and the phasing result is output to the terminal 12-1. Therefore, for the sampling period T of the received signal,
If 2T<3τ<3T, each element has three layers of S/H circuits as shown in Figure 4a, and each element has three layers of control signal sets _C11 to C as shown in Figure 4b. ₁₄ , _C21
By phasing ~C ₂₄ and C ₃₁ ~C ₃₄ , each S/
The sampling period of the H circuit can be set to 3T.

That is, the control signals C ₂₁ to C ₂₄ and C ₂₀ of the second layer are each delayed by T with respect to the first layer, and the control signals C ₃₁ to _{C 34} and C ₃₀ of the third layer are delayed by 2T. . 2
The phasing and addition results of the 3rd and 3rd layers are held in S ₂₀ and S ₃₀ and output at the timing of CW ₅ and CW ₆ , respectively.
The phasing result is output at the period T to the output terminal 12-1.

Even when phasing N elements is performed using an M-layer S/H circuit, the above configuration can be extended in the same manner.

FIGS. 5a and 5b are diagrams showing a second embodiment of the present invention, in which a serial addition multilayer phasing method is applied to the conventional serial addition multilayer phasing method shown in FIG. 3. Figure 2 shows the configuration and timing of control signals. Here, to simplify the explanation, a case will be described in which received signals of three elements are phased by a two-layer S/H circuit. S ₁₁ ~ S ₂₃ are S/H circuits, W ₁₁ ~
W ₂₃ is a switch, and the others are the same as in Figure 3a. In Figure 5b, C ₁₁ to C ₂₃ are S/H circuits.
The hold times of S ₁₁ to S ₂₃ are shown, and CW ₁₁ to _{CW 23} are the ON times of switches W ₁₁ to _{W 23} . τ is the inter-element delay time for obtaining the deflection angle θ, and T is the sampling period.

The received signal of element 1 is sampled and held by the S/H circuit _S11 at the timing of _C11 , and is sent to the switch _W11 at the timing of _CW11 delayed by the inter-element delay τ.
turns ON, and the adder 11-1 holds the result of addition with the signal of element 2 in _S12 . Again, the signal held in S ₁₂ is turned on at the timing of CW ₁₂ , and the adder _11-2 adds the signal to the signal of element 3. The result is held in S ₁₃ , and after the settling time Δτ, the switch W 12 is turned on. When _W13 is turned on, the phasing result is output to the output terminal 12-1.

Here, if T<τ<2T with respect to the sampling period T of the received signal, the S/H circuit is provided in two layers for each element as shown in Fig. 5a, and as shown in Fig. 5b. The signals from each element are combined into two layers of control signals.
By sampling and holding C ₁₁ to C ₁₃ and C ₂₁ to _{C 23} and adding them in series, the sampling period of each S/H circuit can be set to 2T.

That is, the control signals C ₂₁ to _{C 23} of the second layer are each delayed by T with respect to the first layer, and the phasing result held in S ₂₃ is output to the output terminal 12-1 at the timing of CW ₂₃ . be done. In the end, output terminal 12-
In No. 1, the phasing result is output at a period T, and sampling can be performed at a shorter period due to inter-element delay.

The above configuration can be similarly extended to a serial addition M layer type for N elements.

〔Effect of the invention〕

As described above, according to the present invention, the phasing delay of each array element is configured by an S/H circuit, and by having a plurality of S/H circuits and changeover switches for each element in multiple layers, the S/H circuit 1 It is possible to reduce the per-unit sampling rate, achieve phasing with a delay time longer than the sampling period of the received signal, and obtain a large deflection angle even for high-frequency ultrasonic waves. Therefore,
The trapezoidal field of view obtained by the phaser of the present invention has a large aperture and a large deflection angle, compared to conventional linear scan or sector scan.
In addition, it is possible to increase the ultrasonic frequency to a higher frequency.
It is expected that it will greatly contribute to diagnosis.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of a trapezoidal field of view, Fig. 2a is a diagram showing the configuration of a conventional parallel receiving phaser, Fig. 2b is an explanatory diagram of its operation, and Fig. 3a is a conventional serial addition type FIG. 3b is a diagram showing the configuration of the receiving phaser; FIG. 3b is a diagram explaining its operation; FIG. 4a is a diagram showing an embodiment of the present invention;
FIG. 5b is an explanatory diagram of the operation, FIG. 5a is a diagram showing another embodiment, and FIG. 5b is an explanatory diagram of the operation. S ₁ , S ₂ , ..., S _N ... Sample and hold circuit,
11-1, 11-2, 11-3... Adder, C ₁ ,
C ₂ , C ₃ , ..., C _N ... timing signal.

Claims (1)

[Claims] 1. N that receives reflected sound waves from a target as a group.
In an ultrasonic receiving wave phasing circuit, each of the ultrasonic receiving wave phasing circuits has a signal holding means connected to each array element, and sampling and holding each received signal, and an adding means adding the signals held in the signal holding means. It has a plurality of (M) signal holding means connected in parallel per array element, and as a whole, M
forming a group of signal holding means, each of the M groups of signal holding means starts sampling with a predetermined time (T) difference from each other, and each of the M signal holding means Predetermined time (T)
An ultrasonic receiving phasing circuit characterized in that it operates at a sampling period given by the product (MT) of the number (M) of signal holding means connected in parallel for each of the above-mentioned array elements. 2. Each of the N array elements is provided with a signal holding means that samples and holds the received signal, and each signal holding means collects the received signal of the array element concerned and the received signal held of the adjacent array element. In an ultrasonic receiving phasing circuit that delays and adds the received signals of the N array elements that receive reflected sound waves from the target as a group, each array element is Each element has a plurality of signal holding means (M pieces), forming M groups of signal holding means as a whole, and each of the M groups of signal holding means has a predetermined time (T) difference from each other. and starts sampling, and each of the M signal holding means calculates the product ( An ultrasonic receiving phasing circuit characterized by operating at a sampling period given by MT).