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JPH0575415B2 - - Google Patents
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JPH0575415B2 - - Google Patents

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Publication number
JPH0575415B2
JPH0575415B2 JP58224197A JP22419783A JPH0575415B2 JP H0575415 B2 JPH0575415 B2 JP H0575415B2 JP 58224197 A JP58224197 A JP 58224197A JP 22419783 A JP22419783 A JP 22419783A JP H0575415 B2 JPH0575415 B2 JP H0575415B2
Authority
JP
Japan
Prior art keywords
delay means
variable delay
sample
ultrasonic
array element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58224197A
Other languages
Japanese (ja)
Other versions
JPS60116342A (en
Inventor
Shinichi Kondo
Toshio Ogawa
Shinichiro Umemura
Kageyoshi Katakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Healthcare Manufacturing Ltd
Original Assignee
Hitachi Ltd
Hitachi Medical Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Medical Corp filed Critical Hitachi Ltd
Priority to JP22419783A priority Critical patent/JPS60116342A/en
Publication of JPS60116342A publication Critical patent/JPS60116342A/en
Publication of JPH0575415B2 publication Critical patent/JPH0575415B2/ja
Granted legal-status Critical Current

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  • Ultra Sonic Daignosis Equipment (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、電子走査形超音波断層装置の受波整
相回路の構成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the configuration of a wave receiving phasing circuit of an electronic scanning ultrasonic tomography apparatus.

〔発明の背景〕[Background of the invention]

従来の受波整相器の構成を以下に図を用いて説
明する。第1図は超音波断層装置の台形視野を表
わす。同図において区間1〜2はリニア部、区間
3〜4〜5は偏向角θの傾斜部、6は偏向角−θ
の傾斜部の一本の走査線を表わす。
The configuration of a conventional receiving phaser will be explained below using the drawings. FIG. 1 represents a trapezoidal field of view of an ultrasonic tomography device. In the figure, sections 1 to 2 are linear sections, sections 3 to 4 to 5 are inclined sections with a deflection angle of θ, and 6 is a deflection angle of -θ.
represents one scanning line of the slope of .

かかる図のように超音波ビームを偏向させるた
めには、各配列素子の送波受波信号の位相制御が
必要となる。第2図aは偏向角θ方向からの受波
信号を整相する回路構成を表わした図である。
1,2,3,……,Nは配列素子、10−1〜1
0−Nはサンプルホールド回路、11−1は加算
器、12−1は出力端子である。C1〜CNおよび
CAは制御信号である。AA′は偏向角θの受波同
位相面であり、各配列素子の入力信号を同位相と
して整相加算するためには、第i素子の入力信号
を(N−i)τだけ遅延させた後、全素子の信号
を加算する必要がある。ここで、τは素子間の遅
延時間で、次式で与えられる。
In order to deflect the ultrasonic beam as shown in the figure, it is necessary to control the phase of the transmitted and received signals of each array element. FIG. 2a is a diagram showing a circuit configuration for phasing the received signal from the direction of the deflection angle θ.
1, 2, 3, ..., N are array elements, 10-1 to 1
0-N is a sample hold circuit, 11-1 is an adder, and 12-1 is an output terminal. C 1 ~ C N and
C A is a control signal. AA′ is the receiving phase plane with the deflection angle θ, and in order to phase and add the input signals of each array element with the same phase, the input signal of the i-th element is delayed by (N-i)τ. After that, it is necessary to add the signals of all the elements. Here, τ is the delay time between elements, and is given by the following equation.

τ=dsinθ/v ……(1) ここで、θは偏向角、dは素子間隔、vは音速
である。
τ=dsinθ/v (1) Here, θ is the deflection angle, d is the element spacing, and v is the speed of sound.

上記のような信号遅延を実現するために、各配
列素子のサンプルホールド回路10−1〜10−
Nに第2図bで示した制御信号を与えればよい。
すなわち、制御信号C1は送波パルスのタイミン
グと同一であり、制御信号C2〜CNおよびCAは、
C1よりそれぞれ、τ〜(N−1)τおよびτA遅延
している。但し、τA>(N−1)τである。各素
子1〜Nに入力した受波信号はサンプルホールド
回路10−1〜10−Nにより、それぞれ制御信
号C1〜CNのタイミングで保持され、加算器11
−1によりCAのタイミングで加算される。
In order to realize the signal delay as described above, sample and hold circuits 10-1 to 10- of each array element are used.
The control signal shown in FIG. 2b may be applied to N.
That is, the control signal C 1 is the same as the timing of the transmission pulse, and the control signals C 2 to C N and C A are
τ~(N-1)τ and τA are delayed from C1 , respectively. However, τ A >(N-1) τ. The received signals input to each element 1 to N are held by sample and hold circuits 10-1 to 10-N at the timing of control signals C 1 to C N , respectively, and are sent to an adder 11.
-1 is added at the timing of C A.

以上のように構成された従来の受波整相器で
は、第i素子のサンプルホールド回路10−iの
ホールド時間(遅延時間)は(N−i)τであ
り、最大のホールド時間(N−1)τはサンプリ
ング周期T以下である必要がある。したがつて、
素子間遅延は τ<T/N−1 ……(2) となり、すなわち偏向角θは次式で制限される。
In the conventional receiving phaser configured as described above, the hold time (delay time) of the sample and hold circuit 10-i of the i-th element is (N-i)τ, and the maximum hold time (N- 1) τ must be less than or equal to the sampling period T. Therefore,
The inter-element delay is τ<T/N-1 (2), that is, the deflection angle θ is limited by the following equation.

θ<sin-1vT/d(N−1) ……(3) サンプリング周期Tは超音波周波数によつて決
まるので、偏向角θは配列素子数Nによつて制限
され、Nが大きい場合、θを小さくする必要があ
る。したがつて、従来の受波整相器で第1図に示
したような大きな台形視野を得ることが困難であ
つた。
θ<sin -1 vT/d(N-1) ...(3) Since the sampling period T is determined by the ultrasonic frequency, the deflection angle θ is limited by the number of array elements N, and when N is large, It is necessary to reduce θ. Therefore, it has been difficult to obtain a large trapezoidal field of view as shown in FIG. 1 with the conventional receiving phaser.

〔発明の目的〕[Purpose of the invention]

本発明は、このような従来の受波整相器の問題
点を解決するためになされたもので各配列素子の
整相遅延をサンプルホールド回路で構成し、各サ
ンプルホールド回路の出力信号を順次直列加算す
ることによつて、サンプリング周期よりも長く遅
延した信号を整相し、大きな偏向角を得る超音波
受波整相回路を提供することを目的とする。
The present invention was made in order to solve the problems of the conventional receiving phasing device.The phasing delay of each array element is configured with a sample and hold circuit, and the output signal of each sample and hold circuit is sequentially processed. It is an object of the present invention to provide an ultrasonic reception phasing circuit that can phase signals delayed longer than the sampling period by serial addition and obtain a large deflection angle.

〔発明の概要〕[Summary of the invention]

以下、図を用いて本発明の実施例を詳細に説明
する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第3図aは、本発明による直列加算型受波整相
器の構成を示す図であり、13−2〜13−N
は、2入力の信号加算器、15−2〜15−Nは
サンプルホールド回路の整定時間を補正するため
の固定微小遅延手段であり、例えばアナログL−
C遅延線やCharge Coupled Device(CCD電荷結
合型素子)などが用いられる。その他は、第2図
aと同一である。
FIG. 3a is a diagram showing the configuration of a series addition type receiving phaser according to the present invention, and 13-2 to 13-N
is a two-input signal adder, and 15-2 to 15-N are fixed minute delay means for correcting the settling time of the sample and hold circuit.
A C delay line, a charge coupled device (CCD charge coupled device), etc. are used. The rest is the same as FIG. 2a.

かかる構成において、各サンプルホールド回路
の整定時間を等しくΔとする。第3図bのごと
く、偏向角が0°で各素子1〜Nに同一時刻に受波
信号を入力した場合、素子1の信号はサンプルホ
ールド回路10−1によつて第3図cのごとく制
御信号C1のタイミングでサンプルホールドされ
る。素子2の受波信号は遅延回路15−2によつ
て、サンプルホールド回路10−1の整定時間Δ
だけ遅延した後、加算器13−2によつて加算さ
れ、サンプルホールド回路10−2の制御信号
C2のタイミングでサンプルホールドされる。以
下同様に、素子Nの受波信号は、遅延回路15−
Nによつて、サンプルホールド回路10−1〜1
0〜(N−1)の整定時間(N−1)Δだけ遅延
した後、加算器13−Nによつて加算された後、
CNのタイミングでサンプルホールドされ、出力
端子12−1に各素子の同位相受波信号の加算結
果を出力する。
In this configuration, the settling time of each sample and hold circuit is set to be equal to Δ. As shown in Figure 3b, when the deflection angle is 0° and the received signal is input to each element 1 to N at the same time, the signal of element 1 is processed by the sample and hold circuit 10-1 as shown in Figure 3c. Sample and hold is performed at the timing of control signal C1 . The received signal of the element 2 is transmitted by the delay circuit 15-2 to the settling time Δ of the sample-hold circuit 10-1.
after a delay of
Sample and hold is performed at the timing of C2 . Similarly, the received signal of element N is transmitted to delay circuit 15-
Depending on N, the sample and hold circuits 10-1 to 10-1
After being delayed by a settling time (N-1)Δ of 0 to (N-1), the signals are added by the adder 13-N, and then
It is sampled and held at the timing of C N , and outputs the addition result of the in-phase received signals of each element to the output terminal 12-1.

偏向角がθの場合は、各素子間の遅延時間を
(τ+Δ)として、第3図dに示したタイミング
でサンプルホールド回路10−1〜10−Nを制
御すればよい。但し、Tはサンプリング周期、τ
は(1)式で与えられる。
When the deflection angle is θ, the sample and hold circuits 10-1 to 10-N may be controlled at the timing shown in FIG. 3d with the delay time between each element set as (τ+Δ). However, T is the sampling period, τ
is given by equation (1).

このような構成によれば、例えば素子1の次の
サンプリング時刻は素子2のサンプルホールド回
路10−2の制御信号C2より微小時間ΔTだけ遅
れていればよい。したがつて、各素子間の遅延時
間τの制限は、 τ<T−Δ−ΔT ……(4) となり、Δ、ΔT≪Tであるから、最大の素子間
遅延量τmaxTと設定することができる。これ
は(2)式で制限される従来の受波整相器に比べて
(N−1)倍長い遅延時間を整相できることにな
る。
According to such a configuration, for example, the next sampling time of element 1 only needs to be delayed from the control signal C2 of sample hold circuit 10-2 of element 2 by a minute time ΔT. Therefore, the limit on the delay time τ between each element is τ<T-Δ-ΔT...(4) Since Δ, ΔT<<T, the maximum inter-element delay amount τmaxT can be set. can. This means that it is possible to phase the delay time which is (N-1) times longer than that of the conventional receiving phaser which is limited by equation (2).

また、偏向角θの制限は、 θ<sin-1vT/d ……(5) で与えられ素子数Nにかかわらず、サンプリング
周期Tと素子間隔dによつて決まる。したがつ
て、Nを増加し大口径で送受信しても、従来に比
べて十分大きな偏向角を得ることができる。
Further, the limit on the deflection angle θ is given by θ<sin −1 vT/d (5) and is determined by the sampling period T and the element spacing d, regardless of the number N of elements. Therefore, even if N is increased and transmission/reception is performed with a large aperture, a sufficiently large deflection angle can be obtained compared to the conventional one.

第4図aおよびbは、本発明の第2の実施例を
示す図である。
Figures 4a and 4b show a second embodiment of the invention.

14−2〜14−Nはサンプルホールド回路、
C2′〜CN′は制御信号であり、他は第3図aと同一
である。第4図bは制御信号C1〜CNおよびC2′〜
CN′のタイミングを表わした図であり、τは偏向
角θを得るための素子間遅延時間、Tはサンプリ
ング周期である。
14-2 to 14-N are sample and hold circuits,
C 2 ' to C N ' are control signals, and the others are the same as in FIG. 3a. FIG. 4b shows the control signals C 1 to C N and C 2 ′ to
It is a diagram showing the timing of C N ', where τ is the inter-element delay time for obtaining the deflection angle θ, and T is the sampling period.

ここで、各素子1〜Nに入力した受波信号はサ
ンプルホールド回路10−1および14−2〜1
4−Nにより、それぞれ制御信号C1およびC2′〜
CN′のタイミングで保持される。素子1と2の信
号は、加算器13−2で加算された後、サンプル
ホールド回路10−2によつて14−2の整定時
間ΔだけC2′よりも遅れた時刻C2のタイミングで
サンプルホールドされる。素子1,2の加算信号
は、素子3の信号と加算器13−3で加算された
後、サンプルホールド回路10−3によつてC3′ より2Δだけ遅れた時刻C3のタイミングでサンプ
ルホールドされ、以下同様の動作を繰返すことに
より、サンプルホールド回路10−NはCNのタ
イミングで全素子からの受波信号の整相加算信号
をサンプルホールドし、出力端子12−1に出力
する。
Here, the received signals input to each element 1 to N are sample-and-hold circuits 10-1 and 14-2 to 1
4-N respectively control the control signals C 1 and C 2 ′~
It is held at the timing of C N ′. The signals of elements 1 and 2 are added by an adder 13-2, and then sampled by a sample-hold circuit 10-2 at a time C 2 that is delayed from C 2 ' by a settling time Δ of 14-2 . will be held. The added signals of elements 1 and 2 are added with the signal of element 3 in an adder 13-3, and then sampled and held by a sample-and-hold circuit 10-3 at a time C3 delayed by 2Δ from C3 ' . By repeating the same operation, the sample-and-hold circuit 10-N samples and holds the phased sum signal of the received signals from all the elements at the timing C N , and outputs it to the output terminal 12-1.

この実施例においても、第1の実施例と同様に
各素子間の遅延時間τの制限は、(4)式で与えられ
る。したがつて、偏向角θについては(5)式の関係
となり、第1実施例と同様の効果が得られる。
In this embodiment, as in the first embodiment, the limit on the delay time τ between each element is given by equation (4). Therefore, regarding the deflection angle θ, the relationship is expressed by equation (5), and the same effects as in the first embodiment can be obtained.

以上の説明において、超音波ビームの受波偏向
角は、便宜上メインビームの方向について説明し
たが、超音波ビームを集束するために、配列素子
の受波整相する場合にも、本発明が適用可能であ
ることは明らかである。
In the above explanation, the reception deflection angle of the ultrasound beam is explained in terms of the direction of the main beam for convenience, but the present invention is also applicable to the case of phasing the reception of the array element in order to focus the ultrasound beam. It is clearly possible.

〔発明の効果〕〔Effect of the invention〕

以上述べた如く本発明によれば、各配列素子の
整相遅延をサンプルホールド回路で構成し、その
出力信号を順次直列加算することによつて、サン
プリング周期よりも長く遅延した信号を整相する
ことが可能となる。また、最大遅延時間は、配列
素子数には上らないため、本整相器により得られ
る台形視野は、従来のリニアスキヤンまたはセク
タスキヤンに比し、大口径で偏向角の大きな広視
野となり、診断上大いに寄与することが期待され
いる。
As described above, according to the present invention, the phasing delay of each array element is configured by a sample-hold circuit, and the output signals are sequentially added in series, thereby phasing a signal delayed longer than the sampling period. becomes possible. In addition, since the maximum delay time does not increase with the number of array elements, the trapezoidal field of view obtained by this phaser has a large aperture and a large deflection angle compared to conventional linear scan or sector scan. It is expected that it will greatly contribute to diagnosis.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は台形視野の説明図、第2図aは従来の
受波整相器の構成を示す図、第2図bはその動作
説明図、第3図aは本発明の一実施例を示す図、
第3図b,cおよびdはその動作説明図、第4図
aは本発明の他の実施例を示す図、第4図bはそ
の動作説明図である。
Fig. 1 is an explanatory diagram of a trapezoidal field of view, Fig. 2a is a diagram showing the configuration of a conventional receiving phaser, Fig. 2b is an explanatory diagram of its operation, and Fig. 3a is an illustration of an embodiment of the present invention. The figure shown,
3b, c and d are diagrams explaining the operation, FIG. 4a is a diagram showing another embodiment of the present invention, and FIG. 4b is a diagram explaining the operation.

Claims (1)

【特許請求の範囲】 1 連続したN個の配列する振動子素子の各素子
の送波または受波信号の振巾、位相を制御するこ
とにより超音波ビームを偏向させ断層像を得る超
音波断層装置に用いる超音波受波整相回路におい
て、前記超音波ビームの偏向角に依存する遅延を
整相するためのサンプホールド回路からなる可変
遅延手段と、前記可変遅延手段の整定時間を補正
するための固定微小遅延手段と有し、前記素子の
第1番目に配列する第1配列素子に前記可変遅延
手段が接続され、前記素子の第n(n=2、3、
…、N)番目に配列する第n配列素子には前記固
定微小遅延手段が接続され前記固定微小遅延手段
の出力端は2入力端子をもつ加算手段の一方の入
力端子に接続され前記加算手段の出力端子が前記
可変遅延手段が接続され、前記第n配列素子に接
続された前記加算手段の他方の入力端子は前記第
(n−1)配列素子に接続された前記可変遅延手
段の出力端に接続され、前記各素子の前記可変遅
延手段の出力を順次直列加算することにより、各
素子における受波信号のサンプリング周期よりも
長く遅延した受波信号を整相することを特徴とす
る超音波受波整相回路。 2 前記固定微小遅延手段がアナログL−C遅延
線、電荷結合型素子、又はサンプルホールド回路
のいずれかなることを特徴とする特許請求の範囲
第1項記載の超音波受波整相回路。
[Claims] 1. Ultrasonic tomography in which a tomographic image is obtained by deflecting an ultrasound beam by controlling the amplitude and phase of the transmitted or received signal of each element of N consecutively arranged transducer elements. In an ultrasonic reception phasing circuit used in the apparatus, a variable delay means comprising a sample and hold circuit for phasing a delay depending on the deflection angle of the ultrasonic beam, and a settling time of the variable delay means for correcting the settling time of the variable delay means. The variable delay means is connected to the first array element arranged first of the elements, and the variable delay means is connected to the nth (n=2, 3,
..., N)th array element is connected to the fixed minute delay means, and the output terminal of the fixed minute delay means is connected to one input terminal of the addition means having two input terminals. The output terminal of the adding means is connected to the variable delay means, and the other input terminal of the adding means is connected to the nth array element, and the other input terminal is connected to the output terminal of the variable delay means connected to the (n-1)th array element. The ultrasonic receiver is characterized in that the received signal delayed longer than the sampling period of the received signal in each element is phased by sequentially adding the outputs of the variable delay means of the connected elements in series. Wave phasing circuit. 2. The ultrasonic receiving phasing circuit according to claim 1, wherein the fixed minute delay means is any one of an analog LC delay line, a charge-coupled device, or a sample-and-hold circuit.
JP22419783A 1983-11-30 1983-11-30 Ultrasonic receiving phasing circuit Granted JPS60116342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22419783A JPS60116342A (en) 1983-11-30 1983-11-30 Ultrasonic receiving phasing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22419783A JPS60116342A (en) 1983-11-30 1983-11-30 Ultrasonic receiving phasing circuit

Publications (2)

Publication Number Publication Date
JPS60116342A JPS60116342A (en) 1985-06-22
JPH0575415B2 true JPH0575415B2 (en) 1993-10-20

Family

ID=16810040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22419783A Granted JPS60116342A (en) 1983-11-30 1983-11-30 Ultrasonic receiving phasing circuit

Country Status (1)

Country Link
JP (1) JPS60116342A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0655220B2 (en) * 1986-05-01 1994-07-27 三井造船株式会社 Artificial bone for implant

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259974A (en) * 1975-11-12 1977-05-17 Hitachi Medical Corp Method of controlling ultrasonic vibrator and device therefor
JPS52113623A (en) * 1976-03-19 1977-09-22 Hitachi Medical Corp Electronic scanning ultrasonic deflection system
JPS58141142A (en) * 1982-02-17 1983-08-22 株式会社日立メディコ Ultrasonic wave receiving and deflecting circuit

Also Published As

Publication number Publication date
JPS60116342A (en) 1985-06-22

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