JPH056944B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation circuit that demodulates a digitally modulated signal, and more particularly to a circuit that demodulates a four-phase phase modulated signal by delay detection.

[Prior Art] Conventionally, this type of demodulation circuit is generally configured as shown in FIG.

In the figure, 1 is a distributed delay circuit, 2 is a hybrid, 3a and 3b are mixer circuits, 4 is a phase shifter,
110 is a hybrid, and 111 and 112 are delay circuits.

Further, 5 is an input received signal, 6a, 6b are demodulated data signals, 51, 52, 53 are received signals, 70,
71 is a reference signal, and 72 is an orthogonal reference signal.

A digitally modulated input reception signal 5 is supplied to this demodulation circuit. This signal 5
is the first received signal 5 in the hybrid 2
1, a second received signal 52, and a third received signal 53, and outputted to the distribution delay circuit 1, the first mixer circuit 3a, and the second mixer circuit 3b, respectively.

In the conventional device, the distribution delay circuit 1 is composed of a hybrid 110 that divides an input signal into two, a delay circuit 111, and a delay circuit 112.

Then, the distribution delay circuit 1 receives the first received signal 5.
1 is divided into two and further delayed, and the delayed signal is used as a first reference signal 70 for performing delayed detection.
and is output as the second reference signal 71.

In the phase shifter 4, the second reference signal 71
is subjected to a phase shift of π/2 in order to demodulate the four-phase phase modulation signal, and is output as an orthogonal reference signal 72.

The first reference signal 70 and orthogonal reference signal 72 obtained in this way are outputted to the first mixer circuit 3a and the second mixer circuit 3b, respectively.
A first demodulated data signal 6a and a second demodulated data signal 6b are obtained.

[Problems to be Solved] As described above, in the conventional demodulation circuit, the distribution delay circuit 1 is connected to the hybrid 110 and the delay circuits 111, 1.
It consists of 12.

Therefore, as the delay used for delayed detection, it is necessary to accurately perform a phase delay of ±2n-1/4π (where n=1, 2, 3, . . . ) in addition to the delay equivalent to one bit of the data signal.

Therefore, in the past, a delay of approximately one bit was performed and then an adjustment circuit was provided to obtain the optimum delay amount.

However, in this case, the circuit configuration becomes complicated and requires fine adjustment, which poses a problem in that it becomes an obstacle to miniaturization and cost reduction of the device.

The present invention has been made in view of such conventional problems, and its purpose is to realize a compact and low-cost demodulation circuit.

[Means for Solving Problems] In order to achieve the above object, the present invention provides a hybrid circuit that distributes a digitally modulated input received signal into a first received signal, a second received signal, and a third received signal. a distribution delay circuit that divides the first received signal into two, further delays the signal, and outputs a first reference signal and a second reference signal for delayed detection; a first mixer circuit that obtains a first demodulated data signal from the second received signal and the first reference signal; and a third received signal. and a second mixer circuit that obtains a second demodulated data signal from the output signal of the transporter, wherein the distribution delay circuit includes a first mixer circuit that obtains a second demodulated data signal from a first received signal. formed using a surface acoustic wave device including an interdigital electrode, a second interdigital electrode that outputs the first reference signal, and a third interdigital electrode that outputs the second reference signal, In the surface acoustic wave device, the first received signal inputted from the first interdigital electrode is transmitted to the first and second references from the second and third interdigital electrodes arranged at different positions. The signals output as signals and propagating between the first interdigital electrode and the second interdigital electrode and between the first interdigital electrode and the third interdigital electrode are each a data signal. Each interdigital electrode is arranged so that a delay equivalent to 1 bit is applied and at the same time a phase delay of ±2n-1/4π (where n=1, 2, 3...) is applied. do.

[Example] Next, a preferred example of the present invention will be described based on the drawings. Incidentally, the same reference numerals are given to the members corresponding to those of the conventional device shown in FIG. 2, and the explanation thereof will be omitted.

A preferred embodiment of the invention is shown in FIG.
In the device of the embodiment, the distribution delay circuit 1 is formed using a surface acoustic wave (hereinafter abbreviated as SAW) device 11.

This SAW device 11 includes a first interdigital electrode 101 that serves as an input terminal, a second interdigital electrode 102 that serves as an output terminal, and a third interdigital electrode 10 that serves as an output terminal.
It has 3.

The signals propagating between the first interdigital electrode 101 and the second interdigital electrode 102 and between the first interdigital electrode 101 and the third interdigital electrode 103 each contain data. Each interdigital electrode 1 is arranged so that a delay equivalent to 1 bit of the signal is applied and at the same time a phase delay of ±2n-1/4π (where n=1, 2, 3...) is applied.
01, 102, and 103 are arranged.

Hereinafter, each interdigital electrode will be abbreviated as IDT. This embodiment has the above configuration, and its operation will be explained next.

First, when the digitally modulated received signal 5 is input, the signal 5 hybrid circuit 2 converts the first received signal 51, the second received signal 52,
It is distributed to the third received signal 53.

The first received signal 51 is input to the distribution delay circuit 1 composed of the SAW device 11. If the amount of delay necessary for delayed detection is T, then the amount of delay T is expressed as: T=To±2n−1/4π To: amount of delay for 1 bit of data n: 1, 2, 3, . . .

The first time is when n=2 and T=To+(3/4)
It is written as π.

The signal input to IDT 101 becomes a SAW signal and propagates in both directions of IDT 102 and IDT 103.

Each IDT 102 and IDT 103 are placed apart by a distance that causes a delay of T in the SAW signal propagated from the IDT 101.

The signals thus delayed are output from the distribution delay circuit 1 as a first reference signal 70 and a second reference signal 71.

The second reference signal 71 is subjected to a phase delay of π/2 by the phase shifter 4 and becomes an orthogonal base 4 signal 72.

The first mixer circuit 3a receives a second received signal 52.
and the first reference signal 70 are added, and the first data signal 6a is output.

Similarly, the third received signal 53 and the orthogonal reference signal 72 are applied to the second mixer circuit 3b, and the second data signal 6b of the orthogonal component is output.

In this way, demodulation by delayed detection is performed.

[Effects of the Invention] As explained above, the demodulation circuit according to the present invention uses a surface acoustic wave device as a distribution delay circuit, so that the circuit can be formed with one element, so the demodulation circuit can be miniaturized. This is effective in reducing prices.

In addition, since the interdigitated electrodes in the surface acoustic wave device can be formed using printing technology on integrated circuits, they can be formed with great precision, allowing for precise delay amounts to be determined during the manufacture of the surface acoustic wave device. can be obtained at any time.

Therefore, fine adjustment of the amount of delay is not necessary, and manufacturing costs can be reduced, which is also effective in lowering the price of equipment.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing a preferred embodiment of a demodulation circuit according to the present invention, and FIG. 2 is a block circuit diagram of a conventional demodulation circuit. 1: Distribution delay circuit, 2,110: Hybrid circuit, 3a, 3b: Mixer circuit, 4: Phase shifter,
5: Input received signal, 6a, 6b: Demodulated data signal, 11: Surface acoustic wave device, 51, 52, 53:
Received signal, 70, 71: reference signal, 72: orthogonal reference signal, 101, 102, 103: interdigitated electrodes, 111, 112: delay circuit.

Claims (1)

[Claims] 1. A digitally modulated input received signal is
a hybrid circuit that divides the first received signal into a received signal, a second received signal, and a third received signal; a distribution delay circuit that outputs a reference signal; a transfer device that applies a phase delay of π/2 to the second reference signal and outputs the second reference signal; a first mixer circuit that obtains a first demodulated data signal; and a second mixer circuit that obtains a second demodulated data signal from the third received signal and the output signal of the transporter. In the circuit, the distribution delay circuit includes a first interdigital electrode to which the first received signal is input, a second interdigital electrode to output the first reference signal, and a second interdigital electrode to output the second reference signal. A third interdigital electrode is formed using a surface acoustic wave device, and the surface acoustic wave device is configured such that the first received signal input from the first interdigital electrode is placed at a different position. The first and second reference signals are output from the disposed second and third interdigital electrodes, and are output between the first and second interdigital electrodes and between the first and second interdigital electrodes. At the same time, each signal propagating between the electrode and the third interdigital electrode is delayed by an amount equivalent to one bit of the data signal.
A demodulation circuit characterized in that each interdigital electrode is arranged so as to be subjected to a phase delay of ±2n-1/4π (where n=1, 2, 3...).