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JPH0570928B2 - - Google Patents
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JPH0570928B2 - - Google Patents

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Publication number
JPH0570928B2
JPH0570928B2 JP58135906A JP13590683A JPH0570928B2 JP H0570928 B2 JPH0570928 B2 JP H0570928B2 JP 58135906 A JP58135906 A JP 58135906A JP 13590683 A JP13590683 A JP 13590683A JP H0570928 B2 JPH0570928 B2 JP H0570928B2
Authority
JP
Japan
Prior art keywords
silicon
semiconductor
film
amorphous
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58135906A
Other languages
Japanese (ja)
Other versions
JPS6028223A (en
Inventor
Toshio Yoshii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58135906A priority Critical patent/JPS6028223A/en
Publication of JPS6028223A publication Critical patent/JPS6028223A/en
Publication of JPH0570928B2 publication Critical patent/JPH0570928B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2921Materials being crystalline insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3822Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing

Landscapes

  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 この発明は、SOS等絶縁性基板上の半導体結晶
薄膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor crystal thin film on an insulating substrate such as SOS.

〔従来技術とその問題点〕[Prior art and its problems]

絶縁性基板、特に絶縁性単結晶基板上のシリコ
ン膜を用いた集積回路は、その構造上、高密度
化、高速度化の点において半導体基板を用いたも
のよりも有利である。反面、基板上に異種の単結
晶膜を成長させるためシリコン膜には高密度の格
子欠陥が存在するという欠点をもつ。
Integrated circuits using a silicon film on an insulating substrate, particularly an insulating single crystal substrate, are structurally more advantageous than those using a semiconductor substrate in terms of higher density and higher speed. On the other hand, since a single crystal film of a different type is grown on a substrate, the silicon film has the disadvantage of having a high density of lattice defects.

例えばSOS(サフアイア単結晶基板上のシリコ
ン膜)を用いてMOSデバイスを製作しその基本
特性を調べてみるとバルクシリコンのMOSデバ
イスと比べ、ドレーンリーク電流の増加、反転層
移動度の低下が見られる。前者はドレーン側近傍
における生成再結合電流によるものであり、後者
はシリコン膜に散乱中心が多いため、キヤリア担
体が散乱することによつて起こる。そして、これ
らは共に格子欠陥に基因しているものであるため
その大幅な減少及び格子欠陥によつてつくられる
深い準位を電気的に不活性化することが要求され
ている。
For example, when we fabricated a MOS device using SOS (silicon film on a sapphire single crystal substrate) and investigated its basic characteristics, we found an increase in drain leakage current and a decrease in inversion layer mobility compared to bulk silicon MOS devices. It will be done. The former is caused by a recombination current generated near the drain side, and the latter is caused by scattering of carrier carriers because there are many scattering centers in the silicon film. Since these are both caused by lattice defects, it is required to significantly reduce them and to electrically inactivate deep levels created by lattice defects.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体薄膜に存在する格子欠
陥を減少させると共に格子欠陥に基因する深い準
位を電気的に不活性化せしめる効果を与えること
より、すぐれた特性をもつ半導体装置用の絶縁性
基板上の半導体結晶薄膜を得ることにある。
An object of the present invention is to reduce lattice defects existing in semiconductor thin films and to electrically inactivate deep levels caused by lattice defects, thereby providing insulation for semiconductor devices with excellent characteristics. The objective is to obtain a semiconductor crystal thin film on a substrate.

〔発明の概要〕[Summary of the invention]

本発明は絶縁性基板上に形成した半導体結晶薄
膜に該半導体のハロゲン化合物をイオン注入し半
導体膜の一部を非晶質化した後、熱処理により該
非晶質層を再結晶化させ半導体膜に含まれていた
格子欠陥を除去すると共に、イオン注入されたハ
ロゲン原子により格子欠陥における不対電子を不
活性化させることにより半導体薄膜の電気的特性
を向上せしめるものである。
In the present invention, a halogen compound of the semiconductor is ion-implanted into a semiconductor crystal thin film formed on an insulating substrate to make a part of the semiconductor film amorphous, and then the amorphous layer is recrystallized by heat treatment to form a semiconductor film. The electrical properties of the semiconductor thin film are improved by removing the lattice defects contained therein and inactivating the unpaired electrons in the lattice defects by the ion-implanted halogen atoms.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、イオン注入による非晶質化と
その後の熱処理によつて半導体膜中の格子欠陥密
度が大巾に減少すると共に未だ存在する格子欠陥
によつて形成される不対電子はハロゲン原子によ
つて不活性化され、この結果、半導体薄膜の電気
的特性はバルク半導体のそれとほぼ同等のものに
なる。
According to the present invention, the lattice defect density in the semiconductor film is greatly reduced by making it amorphous by ion implantation and the subsequent heat treatment, and the unpaired electrons formed by the still existing lattice defects are removed from the halogen. The electrical properties of the semiconductor thin film are approximately the same as those of the bulk semiconductor.

〔発明の実施例〕[Embodiments of the invention]

本発明の実施例について図面を参照して詳述す
る。第1図に於いて絶縁性基板11として(11
0、2)面を有するサフアイア単結晶基板を用い
た。その上にシリコン(Si)膜12を0.3μm堆積
した。成長方法は化学気相成長法(CVD法)で
あり、その条件を成長温度950℃、成長速度2μ
m/minとすることにより、(001)シリコン単結
晶膜が形成される(第1図a)。次にイオン種と
してシリコンフツ素化合物(SiF+)を選び射影
飛程(Rp)がシリコン膜のほぼ中央部になるよ
う加速電圧を170kVに設定し、ドーズ量2×1015
cm-2の条件においてシリコン膜12へイオン注入
し、シリコン表面側を非晶質化13する。(第1
図b)。次に1000℃、N2ガス雰囲気中において20
分間熱処理を行い、非晶質シリコン層13を固相
エピタキシヤル的に再結晶化せしめる(第1図
c)。
Embodiments of the present invention will be described in detail with reference to the drawings. In FIG. 1, the insulating substrate 11 (11
A sapphire single crystal substrate having a 0, 2) plane was used. A silicon (Si) film 12 with a thickness of 0.3 μm was deposited thereon. The growth method is chemical vapor deposition (CVD), and the conditions are a growth temperature of 950℃ and a growth rate of 2μ.
m/min, a (001) silicon single crystal film is formed (FIG. 1a). Next, a silicon fluorine compound (SiF + ) was selected as the ion species, and the acceleration voltage was set to 170 kV so that the projected range (Rp) was approximately at the center of the silicon film, and the dose was 2 × 10 15
Ions are implanted into the silicon film 12 under cm -2 conditions to make the silicon surface side amorphous 13 . (1st
Figure b). Next, at 1000℃, in a N2 gas atmosphere,
Heat treatment is performed for a minute to recrystallize the amorphous silicon layer 13 in a solid-phase epitaxial manner (FIG. 1c).

このようにして得られた試料を用い、次に
MOS素子を製作しその特性を評価した。試作方
法はよく用いられている多結晶シリコンゲート工
程によつた。Nチヤネル及びPチヤネルMOSト
ランジスタにつき評価を行つた結果、キヤリア移
動度はNチヤネルトランジスタでは800cm2/V・
sec、Pチヤネルトランジスタでは220cm2/V・
secが得られ、従来のSOSMOSトランジスタにお
けるキヤリア移動度450cm2/V・sec(Nチヤネ
ル)、及び180cm2/V・sec(Pチヤネル)を大幅に
上回ることが判明した。また、ドレーンリーク電
流も従来のSOSMOSトランジスタにおける値1
×10-10A/μmから大幅に改善され1×
10-12A/μmになつた。このようにキヤリア移
動度及びドレーンリーク電流が大幅に改良された
理由として、再結晶化したシリコン層における格
子欠陥密度が減少すること及びフツ素が格子欠陥
による不対電子を電気的に不活性化することが考
えられる。
Using the sample thus obtained, next
We fabricated a MOS device and evaluated its characteristics. The prototype was manufactured using a commonly used polycrystalline silicon gate process. As a result of evaluating N-channel and P-channel MOS transistors, the carrier mobility of N-channel transistors is 800 cm 2 /V.
sec, 220cm 2 /V for P channel transistor.
sec, which was found to be significantly higher than the carrier mobility of 450 cm 2 /V·sec (N channel) and 180 cm 2 /V·sec (P channel) in conventional SOSMOS transistors. In addition, the drain leakage current is also 1
Much improved from ×10 -10 A/μm to 1×
It became 10 -12 A/μm. The reason for this significant improvement in carrier mobility and drain leakage current is that the lattice defect density in the recrystallized silicon layer decreases and that fluorine electrically inactivates unpaired electrons due to lattice defects. It is possible to do so.

〔発明の他の実施例〕[Other embodiments of the invention]

上述した工程を経て得られたSOS膜に対し、さ
らにシリコン界面側の結晶性をも改良するため第
2図に示す工程をとることができる。すなわち、
SiFを加速エネルギー350KeV、ドーズ量1×
1015cm-2の条件でシリコン膜22へイオン注入す
る(第2図a)。これによりシリコン界面側が非
晶質23される(第2図b)。次に1000℃N2ガス
雰囲気中で20分間熱処理を行ないシリコン表面側
から非晶質層23を再結晶化する。この工程を経
た後、作られたMOS素子特性ではドレーンリー
ク電流がさらに1桁低下する効果が得られた。
In order to further improve the crystallinity on the silicon interface side of the SOS film obtained through the steps described above, the steps shown in FIG. 2 can be performed. That is,
Acceleration energy of SiF 350KeV, dose 1×
Ions are implanted into the silicon film 22 under conditions of 10 15 cm -2 (FIG. 2a). As a result, the silicon interface side becomes amorphous 23 (FIG. 2b). Next, heat treatment is performed for 20 minutes in a N 2 gas atmosphere at 1000° C. to recrystallize the amorphous layer 23 from the silicon surface side. After going through this process, the characteristics of the MOS device produced had the effect of further reducing drain leakage current by one order of magnitude.

この例においては、界面側、表面側それぞれ一
回ずつイオン注入を行つたが、さらに同様な条件
でイオン注入、熱処理工程を交互にくり返すこと
によつて、より一層の結晶性改善がなされる。
In this example, ion implantation was performed once each on the interface side and the surface side, but crystallinity can be further improved by repeating the ion implantation and heat treatment steps alternately under the same conditions. .

また、本発明実施後のシリコン単結晶膜上にさ
らにシリコン膜をエピタキシヤル成長させること
によつて所望の膜厚のシリコン単結晶膜を得るこ
ともできる。
Furthermore, a silicon single crystal film having a desired thickness can be obtained by further epitaxially growing a silicon film on the silicon single crystal film after implementing the present invention.

基板としては絶縁性単結晶基板であればよく、
サフアイア(a−Al2Os)以外にはスピヌネル
(MgO・Al2Os)、酸化ベリリウム(BeO)、シリ
カ(α−SiO2)、二酸化トリウム(ThO2)など
が挙げられる。
The substrate may be an insulating single crystal substrate;
Other than saphire (a-Al 2 Os), spinunel (MgO.Al 2 Os), beryllium oxide (BeO), silica (α-SiO 2 ), thorium dioxide (ThO 2 ), etc. can be mentioned.

半導体薄膜としてはシリコンの他にジルマニウ
ム、スズ等があげられる。イオン注入条件は所望
の非晶質層を形成できる条件であればよく、イオ
ン種はSiFの他にSiF2、SiF3等のSi−F系、SiCl、
SiCl2のSi−Cl系及び、Si−I系化合物を用いて
もよいことはもちろんである。また他の半導体に
対してもそのハロゲン系化合物を用いればよい。
熱処理温度は再結晶化が起こる温度であればよく
500℃以上で炉処理、あるいはレーザ、電子線等
のエネルギービーム照射であつてもよい。また熱
処理雰囲気はN2ガス、O2ガス、Arガス等の不活
性ガスそれぞれにおいて同様な効果が認められ
た。シリコン膜形成法はCVD法に限らず、真空
蒸着法、分子線エピタキシヤル法などがある。
Examples of the semiconductor thin film include zirmanium, tin, and the like in addition to silicon. The ion implantation conditions may be any conditions that allow the formation of the desired amorphous layer, and the ion species may be Si-F systems such as SiF 2 and SiF 3 , SiCl, SiCl, etc. in addition to SiF.
Of course, Si--Cl and Si--I compounds such as SiCl 2 may also be used. Further, the halogen compound may be used for other semiconductors as well.
The heat treatment temperature may be the temperature at which recrystallization occurs.
Furnace treatment at 500° C. or higher, or energy beam irradiation such as laser or electron beam may be used. Furthermore, similar effects were observed in the heat treatment atmosphere using inert gases such as N 2 gas, O 2 gas, and Ar gas. The silicon film forming method is not limited to the CVD method, but also includes vacuum evaporation method, molecular beam epitaxial method, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜cは本発明の一実施例を説明するた
めの工程断面図、第2図a〜cは本発明の他の実
施例を説明するための工程断面図である。 図において、11,21……サフアイア基板、
12,22……シリコン単結晶膜、13,23…
…非晶質シリコン層、14,24……再結晶化シ
リコン層。
1A to 1C are process sectional views for explaining one embodiment of the present invention, and FIGS. 2A to 2C are process sectional views for explaining another embodiment of the present invention. In the figure, 11, 21... sapphire substrate,
12, 22... Silicon single crystal film, 13, 23...
...Amorphous silicon layer, 14, 24... Recrystallized silicon layer.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁性基板上の半導体薄膜をイオン注入によ
り非晶質化する工程と、その後熱処理により該非
晶質領域を再結晶化せしめる工程とを含んでお
り、かつ該イオン注入におけるイオン種として該
半導体の構成元素のハロゲン化合物を用いること
を特徴とする半導体結晶薄膜の製造方法。
1. It includes the steps of making a semiconductor thin film on an insulating substrate amorphous by ion implantation, and then recrystallizing the amorphous region by heat treatment, and using the semiconductor as the ion species in the ion implantation. A method for producing a semiconductor crystal thin film, characterized by using a halogen compound as a constituent element.
JP58135906A 1983-07-27 1983-07-27 Manufacture of semiconductor crystal thin film Granted JPS6028223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58135906A JPS6028223A (en) 1983-07-27 1983-07-27 Manufacture of semiconductor crystal thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58135906A JPS6028223A (en) 1983-07-27 1983-07-27 Manufacture of semiconductor crystal thin film

Publications (2)

Publication Number Publication Date
JPS6028223A JPS6028223A (en) 1985-02-13
JPH0570928B2 true JPH0570928B2 (en) 1993-10-06

Family

ID=15162589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58135906A Granted JPS6028223A (en) 1983-07-27 1983-07-27 Manufacture of semiconductor crystal thin film

Country Status (1)

Country Link
JP (1) JPS6028223A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09293793A (en) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp Semiconductor device having thin film transistor and manufacturing method thereof
KR100843741B1 (en) 2007-03-31 2008-07-04 동국대학교 산학협력단 Method of manufacturing silicon laminated sapphire thin film

Also Published As

Publication number Publication date
JPS6028223A (en) 1985-02-13

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