JPH0570942B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and in particular,
High-speed, low-consumption gate array LSI consisting of CMOS transistors and bipolar transistors
The present invention relates to a semiconductor integrated circuit device suitable for (Large Scale Integration). [Background of the Invention] Gate array LSI is a method of manufacturing LSIs that have the desired electrical circuit behavior by creating only the mask corresponding to wiring out of the more than 10 photomasks used when manufacturing LSIs according to the developed product. It is something to do.
It is said that the concept of this master slice method has been around since the 1960s. Figure 1 shows the configuration of the gate array LSI. The semiconductor chip 10 has a bonding pad and an input/output circuit area 14 on its outer periphery, and inside thereof, a basic cell row 12 in which basic cells 11 made of elements such as transistors are arranged in the x direction is repeatedly arranged in a y direction with a wiring area 13 in between. The configuration is such that they are arranged in parallel in the direction. In order to obtain a desired electrical circuit operation, one or several adjacent basic cells 11 are connected to form a NAND gate, flip-flop, or the like. One LSI is constructed by wiring various logic gates formed by a plurality of basic cells 11 according to a logic diagram. In a conventional CMOS gate array LSI, the basic cell 11 is composed of CMOS transistors.
CMOS circuits have the advantage of low power consumption, but because the transfer conductance of MOS transistors is small, charging and discharging takes time when the load capacitance is large, resulting in slow speed. Furthermore, in the conventional bipolar gate array LSI, the basic cell 11 is composed of a bipolar transistor, a resistor, and the like. In bipolar circuits, the transfer conductance of bipolar transistors is larger than that of MOS transistors, so
Although it has the advantage of not slowing down even when the load capacity increases, it has the disadvantage that it consumes a large amount of electrode because a large current is passed into and out of a low impedance circuit. [Object of the invention] The object of the invention is to eliminate the above-mentioned drawbacks,
The object of the present invention is to provide a semiconductor integrated circuit device that is high speed, has low power consumption, and has a high degree of integration. [Summary of the Invention] The present invention focuses on the low power consumption characteristics of CMOS circuits and the high drive ability characteristics of bipolar circuits, and uses basic cells that can configure bipolar and CMOS composite circuits that combine both devices. The aim is to obtain a semiconductor integrated circuit device with low power consumption at high speed. [Examples of the Invention] The present invention will be described in detail below with reference to Examples. FIG. 2 is an enlarged view of the cell pattern of the basic cell 11. FIG. 3 conceptually shows a sectional view thereof to aid understanding. Identical parts in FIGS. 2 and 3 are designated by the same numbers. In the N well 21 provided on the P-type semiconductor substrate, a PMOS
P ⁺ region 23 and NPN that constitute the transistor
A collector region 24, a base region 25, and an emitter region 26 forming a bipolar transistor are formed. In other words, PMOS in one N-well
It consists of a transistor and an NPN bipolar transistor. By using this in the circuit part where the potential of the collector region 24 is set to the power supply potential VCC, the potential of the substrate of the PMOS transistor (in this case, the N well 21) is fixed at the collector potential of the NPN bipolar transistor, thereby facilitating integration. This is what we aim to do. It is also possible to place it in another N-well. A collector region 27, a base region 28, and an emitter region 29 forming an NPN bipolar transistor are formed in the N well 22. This is used in a circuit portion where the potential of the collector region 27 changes. N-well 21 and N-well 22
Since it is necessary to electrically insulate the area between them with a P-type region 37 that is lowered to the ground potential, it is necessary to separate them by a dimension determined by the withstand voltage or the like. Note that the P-type region 37, which has been lowered to the ground potential, corresponds to the substrate of the NMOS transistor, and an NMOS transistor is placed between the N-wells 21 and 22.
An N ⁺ region 30 forming a transistor is formed. Similarly, N ⁺ constitutes an NMOS transistor.
Regions 31 and 32 are formed. P ⁺ region 33 is provided to lower the potential of P region 37 to ground potential. 35, 36 are PMOS transistors and
The gate electrode made of polysilicon or the like of the NMOS transistor becomes the input part. Both ends of these are provided with bulges (generally called dog bones) so that they can be contacted with the first wiring such as the first layer Al so that input to the basic cell can be made from either the upper side or the lower side of the channel region 13. 34 is two
This is the gate electrode of the NMOS transistor. The output is generally a connector region 27 formed in the N-well 22, but the input sections 35 and 36 and the output section 27 are connected to the second layer of Al running in the y direction in FIG.
The dimensions are the same as the wiring pitch, allowing automatic design (Design Automation, DA). Polymers forming the gate electrodes 35, 36, 34, etc.
There is a first wiring film (not shown) on the Si wiring, and on top of this, a power supply wiring and a first wiring of Al (not shown) are formed with Al etc. in the longitudinal direction parallel to the basic cell row. be done. Here, the first wiring connects within a logic block and between logic blocks. When it is necessary to connect the poly-Si wiring 34 or the like or the diffusion layer 23 to the Al first wiring, a contact hole (hereinafter simply referred to as a contact) is opened in the first insulating film. A second insulating film (not shown) is provided on the first wiring.
However, a second wiring made of Al is further formed thereon so that its longitudinal direction is orthogonal to the basic cell row. 1st
When it is necessary to connect the wiring and the second wiring,
A contact hole (hereinafter referred to as a through hole) is made in the insulating film. There is a third insulating film on the top layer, which protects the transistors and wiring. In a general gate array LSI, the second insulating film, which has through-holes in the first wiring, second wiring, and the necessary parts to connect them, is changed for each product to achieve the desired result.
In many cases, LSI is obtained. In addition, the first wiring and poly-Si
In some cases, the first insulating film, which has contacts provided in areas necessary for connecting the wiring and the diffusion layer, is also changed. By using a basic cell as shown in FIG. 2, it is possible to construct the logic circuits necessary for designing an LSI.
Examples of these will be explained below. Figure 4 shows the applicant's earlier application (patent application 1983-
(No. 188942) This is a 2-input NAND circuit that is an example of a bipolar/CMOS composite circuit. In FIG. 4, 50 is a first NPN bipolar transistor (hereinafter simply referred to as the first NPN) whose collector is connected to the power supply terminal 40 and its emitter is connected to the output terminal 43, and 51 is a collector whose collector is connected to the output terminal 43.
3, a second NPN bipolar transistor (hereinafter simply referred to as second NPN) whose emitter is connected to a fixed potential terminal whose emitter is at ground potential; 41 and 42 are two input terminals; 44 and 45 are respective gates; First and second PMOS transistors (hereinafter simply referred to as first
(referred to as the second PMOS), 46 and 47
In this case, each gate is connected to a different input terminal 41 and 42, and each drain and each source are connected to a second NPN.
51, first and second NMOS transistors (hereinafter simply referred to as the first NMOS and second NMOS) connected in series between the collector and the base, 48, whose gate is connected to the power supply terminal 40, and whose drain and A third NMOS transistor (hereinafter simply referred to as third NMOS) whose source is connected to the base and emitter of the first NPN 50, 49 has a gate connected to the power supply terminal 40 and a drain and source connected to the second NMOS transistor.
A fourth NMOS transistor (hereinafter simply referred to as the fourth
(referred to as NMOS). Table 1 shows the logical operation of the circuit of FIG.

[Table] First, when either of the inputs 41 and 42 is at the "0" level, either the first or second PMOS, 44, 45 is turned on, and the first or second NMOS 46,
47 is turned off. Therefore, the first
The base potential of NPN,50 rises and the first
The NPN, 50 is turned on, and the base and emitter of the second NPN, 51 are short-circuited through the fourth NMOS, 49, which is in the non-saturation region, and the emitter current of the first NPN, 50 is turned off. is charged, and the output 43 becomes "1" level. When both inputs 41 and 42 are at "0" level,
Both the first and second PMOS 44, 45 are turned on, and both the first and second NMOS 46, 47 are turned off. Therefore, the operation is the same as above and the output 43 becomes "1". On the other hand, when both inputs 41 and 42 are at the "1" level, both the first and second PMOS, 44, 45 are turned off, and the first and second NMOS, 46, 47
both are turned on. Therefore, the first NPN,
50 is short-circuited between the base and emitter through the third NMOS, 48, which is in the non-saturation region, and is turned off.
2nd NPN, 51 collectors, 1st between bases,
Since it is shorted through the second NMOS, 46, 47, the base of the second NPN, 51 has the output 43
A current is supplied from the second NPN, 51 is turned on, and the output 43 becomes "0" level. Note that the third and fourth NMOSs 48 and 49 may be simple resistance elements. FIG. 5 shows this two-input NAND circuit constructed using the basic cell shown in FIG. 2. In Figure 5,
□ × marks are contacts, broken lines are first wirings, □ / marks are through holes, and dashed lines are second wirings. Parts that are the same as in FIG. 2 are designated by the same numbers. Furthermore, element numbers are given on the gate electrodes and the like in order to correspond to FIG. 4. First, the first wiring 52 which becomes the VCC power line is connected to the source of the second PMOS, 45 through the contact 53, and to the source of the first PMOS, 45 through the contact 54.
44 to the first source by contact 55.
NPN, collector of 50 and contact 56
are connected to the gate electrodes 34 of the third and fourth NOMS, 48 and 49, respectively. First wiring 5
7 and contacts 59, 58, and 60, the first
Drains of the second PMOS44, 45,
The base of the NPN 50 and the drain of the third NMOS 48 are connected to each other. First wiring 61, 6
2. Contacts 63, 64, 65, 66, 67 connect the emitter of the first NPN 50 and the third
The source of the NMOS 48, the drain of the first NMOS 46, and the collector of the second NPN 51 are connected to each other. Further, the emitter of the first NPN 50 and the collector of the second NPN 51 are connected by a second wiring 68 and through holes 69 and 70.
This is because if this second wiring 68 is not present, the first
The sheet resistance of the drain of the first NMOS 46 enters between the emitter of the NPN 50 and the collector of the second NPN 51, reducing the speed, so this is provided to prevent this. Further, this second wiring 68 is located on a grid of second wirings running in the y direction, thereby minimizing interference with the DA. The source of the second NMOS 47, the drain of the fourth NMOS 49, and the second
The bases of NPN51 are connected. The first wiring 75 serving as a ground potential line is connected to the contact 7
the source of the fourth NMOS 49 by 6,77;
Connected to the emitter of the second NPN 51. P substrate 37 is fixed to ground potential by contact 78 . Regarding the thickness of the wiring such as Al, the first wiring 52, 75 which becomes the power supply line is thick, and the base current is about h _FE
The first wiring 61, 6 through which the emitter current flows twice as much
2 and the second wiring 68 are made thicker than the first wirings 57 and 71 through which the base current flows. In other words, the base wiring is constructed with the minimum line width of the process. In addition, contacts 53, 54, 66, and 72 are
The purpose of each is to reduce contact resistance where there is room for it, reduce the sheet resistance of the drain or source of a MOS transistor, and increase speed. In this way, a 2-input NAND circuit can be constructed. FIG. 6 shows a sectional view of FIG. 5, which constitutes a two-input NAND circuit of the bibolar/CMOS composite circuit of FIG. 4. Element numbers are given in the figure to indicate correspondence with FIG. 4. Wiring is added to the cross-sectional view of FIG. 3 before the wiring process, and further explanation will be omitted. Figure 7 shows the applicant's earlier application (patent application 1983-
(No. 188942) This is a two-input NOR circuit, which is another example of a bibolar/CMOS composite circuit. In FIG. 7, 88 indicates that the collector is the current terminal 9.
0, the first one whose emitter is connected to the output terminal 81
NPN '89 is a second NPN whose collector is connected to the output terminal 81 and whose emitter is connected to a fixed potential terminal whose emitter is ground potential; 79 and 80 are two input terminals;
82 and 83 are first and second NPNs whose gates are respectively connected to different input terminals 79 and 80, and whose sources and drains are connected in series between the collector and base of the first NPN 88, respectively.
The PMOSs 84 and 85 have first and second gates connected to different input terminals 79 and 80, respectively, and drains and sources connected in parallel between the collector and base of the second NPN 89, respectively.
NMOS, 86 is a third NMOS whose gate is connected to the power supply terminal 90, drain and emitter are connected to the base and emitter of the first NPN 88, 87 is a third NMOS whose gate is connected to the power supply terminal 90, and whose drain and emitter are connected to the second NPN 89. The fourth NMOS is connected to the base and emitter of the . Table 2 shows the logical operation of this embodiment.

[Table] First, when both the inputs 79 and 80 are at the "0" level, both the first and second PMOSs 82 and 83 are turned on, and both the first and second NMOSs 84 and 85 are turned off. Therefore, the base potential of the first NPN 88 rises, the first NPN 88 is turned on, and the second NPN 89 is in the non-saturated region.
Since the base and emitter are short-circuited through the NMOS 87 and turned off, the emitter current of the first NPN 88 charges the load and the output 81 becomes the "1" level. When either of the inputs 79 and 80 is at the "1" level, either the first or second PMOS 82 or 83 is turned off, and the first or second NMOS 84 or 85 is turned off.
Either one is turned on. Therefore, the first
The base and emitter of the NPN 88 are short-circuited through the third NMOS 86 in the non-saturation region and turned off, and the base and collector of the second NPN 89 are shorted through the first and second NMOS 84 or 85 which are on. Since it is short-circuited, the base of the second NPN 89 is supplied with current from the output 81 and the second NPN
89 is turned on, and the output 81 becomes "0" level. When both inputs 79 and 80 are at "1" level,
Both the first and second PMOSs 82 and 83 are turned off, and both the first and second NMOSs 84 and 85 are turned on. Therefore, the operation is the same as above, and the output 81 is at the "0" level. FIG. 8 shows this two-input NOR circuit constructed using the basic cell shown in FIG. 2. In the figure, □× marks are contacts, broken lines are first wirings made of Al or the like, □/ marks are through holes, and dashed lines are second wirings made of Al or the like.
Since the details have been explained in FIG. 5, the numbers of the same parts as in FIG. 2 are omitted here to avoid complexity. In order to correspond with FIG. 7, element numbers are given on the gate electrodes and the like. Also, contacts etc. in the same locations as in FIG. 5 are indicated by the same numbers. First, the first PMOS is
The source of 82, the collector of the first NPN 88, and the gate electrodes of the third and fourth NMOS 86 and 87 are
Connected to VCC potential. The second PMOS 8 is connected to the first wiring 91 and the contacts 92, 58, 60.
3 drain, 1st NPN88 base, 3rd
The drain of NMOS86 is connected. First wiring 94, 96, contacts 63, 64, 9
3, 95, 67, the emitter of the first NPN 88, the source of the third NMOS 86, the first, the second
drains of NMOS84 and 85, second NPN8
9 collectors are connected. Furthermore, the second wiring 6
8. Through holes 69 and 70 connect the first
The emitter of NPN88 and the collector of second NPN89 are connected. The reason for providing the second wiring 68 is the same as in the case of the two-input NAND circuit described above.
First wiring 97, contacts 66, 72, 73, 7
4. First and second NMOS 84, 85 sources,
Drain of 4th NMOS87, 2nd NPN89
The base is connected. The source of the fourth NMOS 87 and the second NPN 89 are connected by the first wiring 75 serving as a ground potential line and the contacts 76, 77, and 78.
The emitter and the P substrate 37 are fixed at ground potential. In this way, a 2-input NOR circuit is constructed. FIG. 9 shows an inverter circuit which is another example of a bibolar/CMOS composite circuit suitable for the basic cell of this embodiment. In FIG. 9, 107 is a first NPN whose collector is connected to the power supply terminal 100 and its emitter is connected to the output terminal 99, and 108 is a fixed potential terminal whose collector is connected to the output terminal 99 and whose emitter is ground potential. The second NPN, 101 and 102 connected to
first and second PMOSs, 10 whose gates are connected to the input terminal 98 and whose sources and drains are respectively connected to the collector and base of the first NPN, 107;
3 and 104 have their gates connected to the input terminal 98, and their drains and sources connected to the second NPN, 108, respectively.
first and second connected to the collector and base of
NMOS, 105 has a gate connected to the power supply terminal 100
, the drain and source are respectively first NPN,
The third one connected to the base and emitter of 107
NMOS, 106 has a gate connected to the power supply terminal 100,
The drain and source are respectively the second NPN, 1
The fourth one connected to the base and emitter of 08
It is NMOS. Table 3 shows the operation of the circuit of FIG.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to manufacture an LSI having cells that can be configured in high density, thereby realizing a high speed, low power consumption, and highly integrated semiconductor integrated circuit device.

[Brief explanation of the drawing]

Fig. 1 is a chip diagram of a gate array LSI, Fig. 2 is a diagram showing a plane pattern of a basic cell showing an embodiment of the present invention, Fig. 3 is a vertical structure diagram of Fig. 2, and Fig. 4 is a bipolar LSI chip diagram. 2 which is an example of a CMOS composite circuit
Input NAND circuit diagram, Figure 5 is a diagram showing a planar pattern configuring the circuit in Figure 4 using the basic cell shown in Figure 2, Figure 6 is a vertical structure diagram of Figure 5, and Figure 7 is a bipolar 2 inputs which is an example of CMOS composite circuit
NOR circuit diagram, Figure 8 is a diagram showing a plane pattern configuring the circuit in Figure 7 using the basic cell shown in Figure 2, Figure 9 is an inverter circuit diagram that is an example of a bipolar/CMOS composite circuit, Figure 10 The figure is a plan pattern diagram of the basic cell shown in FIG. 2 configuring the circuit of FIG. 9, FIG. 11 is a plan pattern diagram of the basic cell showing another embodiment of the present invention, and FIG. FIG. 5 is a plan pattern diagram configuring the circuit of FIG. 4 using the basic cells shown in FIG. 11... Basic cell, 21, 22... N well,
23...P ⁺ region of PMOS, 24...Collector region, 25...Base region, 26...Emitter region, 27...Collector region, 28...Base region, 29...Emitter region, 30...NMOS
N ⁺ region, 33...P ⁺ region that fixes the potential of the P substrate.

Claims (1)

[Claims] 1. A plurality of bipolar transistors and a plurality of
In a semiconductor integrated circuit device including a plurality of basic cells each consisting of a MOS transistor, the basic cell is provided on a P-type semiconductor substrate, and includes a first collector region connected to a power supply potential section, a first base region, and the above-mentioned basic cell. a first bipolar transistor comprising a first emitter region provided in a first base region;
A first P+ region constituting a PMOS transistor and a first P+ region for taking an electrode from the first P+ region.
and a second gate electrode, a second collector region, a second base region, and a second emitter region provided in the second base region. a second N-well constituting a second bipolar transistor; and a first N+ region constituting first and second NMOS transistors on the P-type region, the first and second gate electrodes the first N connected to
+ region, a second P+ region for lowering the potential of the P-type region to the ground potential, a second N+ region constituting a third NMOS transistor, and a fourth NMOS transistor.
A third N+ region constituting an NMOS transistor and a third gate electrode for taking a common electrode from the second and third N+ regions are configured; The first, second and third NMOS transistors constituting the No. 4 NMOS transistor
A semiconductor integrated circuit device, characterized in that the P-type region composed of the + region and the second P+ region is arranged between the first and second N-wells. 2. In claim 1, an emitter region of the first bipolar transistor whose one main terminal is connected to a power supply potential section in a semiconductor substrate, and a potential of the one main terminal that changes during rotational operation. The semiconductor integrated circuit device is characterized in that the collector region of the second bipolar transistor is connected to the collector region of the second bipolar transistor by a metal low resistance wiring. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein a plurality of contacts are provided on the first insulating film on the drain or source of at least one of the MOS transistors. 4. The semiconductor integrated circuit device according to claim 1 or 2, wherein the wiring connected to the base region of the bipolar transistor is thinner than the wiring connected to the collector region or the emitter region. 5. The semiconductor integrated circuit device according to claim 1 or 2, characterized in that no base contact is provided between the collector region and emitter region of the bipolar transistor. 6. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that the semiconductor integrated circuit device is a gate array LSI. 7. In claim 1 or 2, the input of the MOS transistor and the output of one main terminal of the bipolar transistor whose potentials change during circuit operation are on a wiring grid. A semiconductor integrated circuit device characterized by: 8. A semiconductor integrated circuit device according to claim 6, characterized in that a bulge that can be contacted with wiring is provided at one or more locations on the gate electrode of the MOS transistor. 9 In claim 6, there are two NPN transistors in the basic cell,
A semiconductor integrated circuit device comprising at least one PMOS transistor and one NMOS transistor pair. 10. A semiconductor integrated circuit according to claim 6, characterized in that passing spaces for one or more logic circuits are provided on both sides of the highest potential electric wiring and the lowest potential power supply wiring that pass over the MOS transistor. Device. 11. A semiconductor integrated circuit device according to claim 6, characterized in that the semiconductor integrated circuit device is configured such that input to the basic cell can be made from either the P-type field effect transistor side or the N-type field effect transistor side.