JPH0570963B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to, for example, a digital AM demodulator that demodulates an AM-modulated video signal.

[Conventional technology]

For example, when transmitting a still image signal using a telephone line, the video signal is written to a frame memory, read out at low speed, and then transferred to a low-frequency carrier wave.
It is transmitted using AM modulation. In order to read the video signal into the frame memory, the video signal is once digitized, read out from the frame memory, and then converted back into an analog signal.

The signal transmitted in this way is
AM demodulation is performed on the low-speed video signal from the signal, and this low-speed video signal is written into a frame memory and read out and played back at normal speed. The demodulated low speed video signal is digitized to write the low speed video signal to the frame memory.

Conventional AM demodulators, for example, have an analog demodulator configuration using diodes, and the analog demodulator demodulates the video signal, which is then digitized using an A/D converter. .

[Problem to be solved by the invention] However, for example, when transmitting a video signal using a telephone line, the carrier wave has a low frequency;
When a conventional AM demodulator is used, the filter for carrier removal after demodulation is required to have steep characteristics. Further, conventional AM demodulators are affected by fluctuations in DC components caused by temperature changes, for example, and cannot perform highly accurate demodulation. Furthermore, when it is necessary to digitize the output after demodulation, two processes are required: AM demodulation and A/D conversion.

Therefore, an object of the present invention is to provide a digital AM demodulator that can perform AM demodulation and A/D conversion without using an analog AM demodulator, does not require a carrier removal filter, and has good temperature characteristics. Our goal is to provide the following.

Another object of the present invention is to provide a digital AM demodulator with improved DC drift.

[Means for solving problems]

The present invention includes a circuit that generates a sampling clock synchronized with the peak value of an input analog AM modulation signal, and an A/D converter that digitizes the AM modulation signal using the sampling clock. The input signal is AM demodulated and digitized by this A/D converter.

The output of the upper bit of the output of this A/D converter is integrated to compensate for DC drift.

[Effect]

Changes in data obtained by sampling the peak value of the AM modulated signal correspond to changes in the amplitude of the AM demodulated signal. Therefore, the present invention provides input analog
It is equipped with a circuit that generates a sampling clock synchronized with the peak value of the AM modulation signal, and an A/D converter that digitizes the AM modulation signal using the sampling clock. By sampling the peak value, an output that is both AM demodulated and digitized is obtained.

When an AM modulated signal is sampled at its peak value and digitized, the upper bits will be inverted every sampling clock if there is no DC drift in this AM modulated signal. However, if DC drift occurs, this inversion of the upper bits will not occur. Therefore, DC drift is compensated by the output obtained by integrating the upper bits.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 indicates an input terminal, and the AM-modulated video signal from the input terminal 1 is passed through a subtraction circuit 2 to, for example, an 8-bit A/D.
It is supplied to the converter 3 and also to the limiter 4. This AM modulated video signal is
For example, a 1700 kHz carrier wave is AM-modulated with a low-speed video signal, and is transmitted via a telephone line from a transmission system configured as shown in FIG.

On the transmitting side, as shown in FIG. 2, the video signal is supplied from a terminal 15 to an A/D converter 16 and digitized. A/D converter 16
The output of is supplied to the frame memory 17. The video data written in the frame memory 17 is read out at a low speed, supplied to the D/A converter 18, and converted back into an analog signal. The output of the D/A converter 18 is supplied to the AM modulation circuit 19,
The 1700kHz carrier wave is AM modulated. The output of the AM modulation circuit 19 is taken out to an output terminal 20 and transmitted via a telephone line. Since the data written to the frame memory 17 is read out at a low speed, this AM transmitted via the telephone line is
The modulated video signal has a narrow band of (1700±800)k
It is in the Hz band.

In Fig. 1, the limiter indicated by 4 is an amplifier with a sufficiently high gain, and from limiter 4, the third
As shown in Figure B, a pulse whose edge coincides with the zero cross point of the input AM modulated video signal (Figure 3A) is output. The output of limiter 4 is supplied to phase comparator circuit 5.

A PLL is configured by a phase comparison circuit 5, a VCO (voltage controlled oscillator) 6, and a 1/2 frequency divider circuit 7.
The output of the VCO 6 is supplied to the phase comparison circuit 5 via the 1/2 frequency divider 7, and the output of the phase comparison circuit 5 is
It is supplied to the VCO 6, and the oscillation frequency of the VCO 6 is controlled. The output shown in FIG. 3C is supplied from the 1/2 frequency divider circuit 7 to the phase comparator circuit 5, and from the VCO 6,
The output shown in FIG. 3D is taken.

The output of the VCO 6 is shifted by 90° via a 90° phase shifter 8, and the output of the 90° phase shifter 8 shown in FIG. 3E is supplied to the A/D converter 3 as a sampling clock. The video signal supplied to the A/D converter 3 via the subtraction circuit 2 is sampled at the falling edge of this sampling clock,
Digitized. The sampling clock is synchronized to the peak value of the input AM modulated video signal at twice the frequency of the carrier wave of the input AM modulated video signal, as shown in FIG. Therefore, the peak value of this AM modulated video signal is sampled and digitized. Changes in data whose peak values are sampled in this manner correspond to changes in the amplitude of the input AM modulated video signal.
Therefore, this AM modulated video signal is digitized by the A/D converter 3, and the AM
It will be demodulated.

The output of A/D converter 3 is supplied to latch 10, and the most significant bit of A/D converter 3 is supplied to integrator 9. The output of the integrator 9 is supplied to the subtraction circuit 2.

The integrator 9 and subtraction circuit 2 compensate for DC drift of the input video signal. That is, when an AM modulated signal is sampled with a peak value, if there is no DC drift in this AM modulated signal, the polarity of the sampled data is inverted for each sample data. The output of the A/D converter 3 is a code such as an offset binary code in which the most significant bit is inverted depending on the polarity. Therefore, if there is no fluctuation in the DC component of the input video signal, the output of the most significant bit of the A/D converter 3 will alternately repeat 1 and 0 for each sample data. Therefore, a low level output and a high level output are alternately supplied to the integrator 9, and the output of the integrator 9 becomes 0.

As the DC level of the AM modulation signal increases, positive data continues. Therefore, the most significant bit of the A/D converter 3 is a series of 1's.
Therefore, a high level output is continuously supplied to the integrator 9, and the output of the integrator 9 becomes a positive value.
The output of the integrator 9 is supplied to a subtraction circuit 2 and subtracted from the video signal supplied from the input terminal 1.
Therefore, the increase in the DC level of the input video signal is compensated for.

Furthermore, when the DC level of the AM modulation signal decreases, even when the peak value of the AM modulation signal is sampled, the polarity of the data does not invert, and negative data continues. Therefore, when the DC level of the input video signal decreases, the most significant bit of the A/D converter 3 is not inverted for each sample data, but becomes a series of 0's. Therefore, integrator 9
is continuously supplied with a low level output, and the output of the integrator 9 becomes a negative value. The output of the integrator 9 is supplied to a subtraction circuit 2 and subtracted from the video signal supplied from the input terminal 1 to compensate for a drop in the DC level of the input video signal.

Latch 10 includes a 90° phase shifter 8 and a 1/2 frequency divider circuit 1.
A latch pulse having a frequency of 1/2 that of the sampling clock is supplied via 1. By this latch pulse, data of either positive or negative polarity of the output data of the A/D converter 3 is taken into the latch 10. The output of the latch 10 is supplied to the frame memory 12, AM demodulated to the frame memory 12,
The data of the digitized video signal is stored.

Even if the DC level fluctuates, the polarity of the data remains inverted in the large amplitude portion. Therefore, the compensation circuit configured as described above cannot compensate for this variation. However, in the large amplitude portion, the influence of DC level fluctuations is small and does not pose a major problem. Furthermore, in order to compensate for the DC level in such a large amplitude portion, instead of the most significant bit of the A/D converter 3, for example, the lower bits thereof may be supplied to the integrator. Furthermore, an adaptive configuration may be used in which the bit for detecting fluctuations in the DC level is switched depending on the input amplitude.

Note that the output of the A/D converter 3 is 2's
Complementary codes may also be used; in this case, when the DC level of the input AM modulated video signal increases, the output of the integrator becomes negative, and the input
When the DC level of the AM modulated video signal drops, the output of the integrator becomes positive. Therefore, DC level compensation is achieved by adding the output of the integrator to the input AM modulated video signal.

Furthermore, in this embodiment, the output of the integrator is fed back to the input signal to compensate for DC drift, but the output of the integrator is digitized and supplied to the digitized output to compensate for DC drift. You can do it like this.

FIG. 4 shows another embodiment of the invention. This embodiment is suitable for application to, for example, a television detection circuit when the frequency of the carrier wave of the input AM modulated signal is high.

In FIG. 4, reference numeral 21 indicates an input terminal, from which a video intermediate frequency signal in which a carrier wave of a video intermediate frequency of 58.75 MHz is AM-modulated is supplied via a subtraction circuit 22 to a sample and hold circuit 23. It is supplied to the limiter 24. The output of the limiter 24 is supplied to a phase comparison circuit 25.

Phase comparator circuit 25, VCO 26, and 1/2 frequency divider circuit 2
7 constitutes a PLL. VCO26
The output of the phase comparator circuit 25 is supplied to the phase comparator circuit 25 via the 1/2 frequency divider circuit 27, and the output of the phase comparator circuit 25 is
It is supplied to the VCO 26, and the oscillation frequency of the VCO 26 is controlled. VCO26 outputs a pulse with a frequency twice the video intermediate frequency, and this output
It is supplied to a 90° phase shifter 28. The 90° shifter 28 outputs a pulse synchronized with the peak value of the video intermediate frequency signal, and this pulse is sent to the 1/n frequency dividing circuit 29.
is supplied to The output of the 1/n frequency divider circuit 29 is supplied to the sample hold circuit 23 and the A/D converter 30 as a sampling clock.
The 1/n frequency divider circuit 29 is a frequency divider circuit with a frequency division ratio of 1/an odd number, and the frequency division ratio is, for example, 1/7.

Using the sampling clock output from the 1/n frequency divider circuit 29, the peak value of the video intermediate frequency signal is sampled and held every predetermined number in the sample hold circuit 23, and is supplied to the A/D converter 30 and digitized. .

As in other embodiments, if the frequency of the carrier wave is sufficiently higher than the frequency of the modulation signal, a configuration may be used in which the peak value is sampled every predetermined number of times instead of sampling all of the peak values of the AM modulation signal. , can demodulate AM modulated signals. In this way, by sampling every predetermined number of times, the frequency of the sampling clock decreases,
There is no need to operate the A/D converter 30 at high speed.

The frequency division ratio n of the 1/n frequency divider circuit 26 is inputted.
It is set to an odd fraction in order to alternately sample the positive and negative peak values of the AM modulated signal. A sampling clock having such a frequency may be generated from the PLL without depending on the 1/n frequency divider circuit 26.

The demodulated digital color television signal is taken out from the output terminal 32, and the A/D
The most significant bit of the output of the converter 30 is the integrator 3.
1. The output of the integrator 31 is sent to the subtraction circuit 2
2, and the output of this integrator 31 compensates for the DC drift of the input signal as in the previous embodiment.

〔Effect of the invention〕

According to this invention, a digital AM demodulates an analog modulated signal and digitizes it.
A demodulator can be realized. In this way, AM demodulation and digitization can be performed without using an analog demodulator, so there is no need for a filter for carrier removal after AM demodulation. Furthermore, according to this invention, A/D
The DC drift of the input AM modulation signal can be compensated for by the output obtained by integrating the upper bits of the output of the converter, and a digital AM demodulator with improved DC drift can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of the transmission side of a video signal transmission system to which an embodiment of the invention is applied, and Fig. 3 is an embodiment of the invention. FIG. 4 is a block diagram of another embodiment of the present invention. 1, 21: input terminal, 2, 22: subtraction circuit,
3, 30: A/D converter, 5, 25: Phase comparison circuit, 6, 26: VCO, 9, 31: Integrator.

Claims (1)

[Scope of Claims] 1. A sampling clock generation circuit that generates a sampling clock synchronized with the peak value of an input analog AM modulation signal; an A/D converter that digitizes the AM modulation signal using the sampling clock; and a circuit that obtains an AM demodulated output of the AM modulated signal based on peak value data of the positive or negative polarity of the A/D converter, which performs AM demodulation of the input analog AM modulated signal and outputs a digitized output. A digital AM demodulator characterized by the following features: 2. A sampling clock generation circuit that generates a sampling clock synchronized with the peak value of the input analog AM modulation signal; an A/D converter that digitizes the AM modulation signal using the sampling clock; and a circuit for obtaining an AM demodulated output of the AM modulated signal based on peak value data of positive or negative polarity, and the most significant bit of the output of the A/D converter or the input analog AM modulated signal has a DC drift. , the DC drift obtained by integrating the upper bits showing the same value in the positive and negative polarity peak value data of the A/D converter is fed back to the input analog AM modulation signal. or means for compensating for the DC drift by digitizing and supplying the data to the output data of the A/D converter; A digital AM demodulator characterized by the following.