JPH0572087B2 - - Google Patents
Info
- Publication number
- JPH0572087B2 JPH0572087B2 JP1109779A JP10977989A JPH0572087B2 JP H0572087 B2 JPH0572087 B2 JP H0572087B2 JP 1109779 A JP1109779 A JP 1109779A JP 10977989 A JP10977989 A JP 10977989A JP H0572087 B2 JPH0572087 B2 JP H0572087B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- magnetic
- forming
- terminal electrode
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Manufacturing Cores, Coils, And Magnets (AREA)
- Coils Or Transformers For Communication (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、積層インダクタの製造方法に係るも
ので、特に端子電極の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a laminated inductor, and particularly to a method for manufacturing a terminal electrode.
〔従来技術〕
電子部品の小形化、薄形化等の要求に伴つて、
インダクタの分野においても巻線を用いない積層
インダクタが用いられるようになつている。この
積層インダクタは、Ni−Zn系フエライト等の磁
性体層と、銀などの導体層を交互に形成され、螺
旋状の導体パターンが磁性体層間から層間に接続
して形成され、閉磁路構造のインダクタとなる。
焼成後、両端面に端子電極が形成される。[Prior art] With the demand for smaller and thinner electronic components,
In the field of inductors as well, laminated inductors that do not use windings have come into use. This laminated inductor has magnetic layers such as Ni-Zn ferrite and conductor layers such as silver formed alternately, and a spiral conductor pattern is formed by connecting between the magnetic layers, creating a closed magnetic circuit structure. It becomes an inductor.
After firing, terminal electrodes are formed on both end faces.
チツプ化の要求を満たすために、第4図のよう
に、端子電極42は対向する両端面と他の面の両
端面側の一部が跨がつて形成される。また、この
端子電極は、フエライトと内部導体の焼成後、焼
付によつて形成されている。 In order to meet the requirements for chipping, the terminal electrode 42 is formed so that both opposing end surfaces and a portion of both end surfaces of the other surface straddle each other, as shown in FIG. Further, this terminal electrode is formed by baking the ferrite and the internal conductor after firing.
しかし、上記のように両端面に端子電極を形成
すると、端子電極間に大きな浮遊容量が発生して
しまう。積層インダクタにおいては0.5〜0.8pF程
度の容量が発生し、自己共振周波数の低下などの
問題を生じる。
However, when terminal electrodes are formed on both end faces as described above, a large stray capacitance is generated between the terminal electrodes. A capacitance of about 0.5 to 0.8 pF is generated in a laminated inductor, which causes problems such as a decrease in self-resonant frequency.
そのため、端子電極を端面の一部のみに形成す
ることも考えられているが、強度的には問題があ
る。 Therefore, it has been considered to form the terminal electrode only on a part of the end face, but this poses a problem in terms of strength.
本発明は、浮遊容量が小さく、かつ十分な強度
を有する端子電極を形成するものである。 The present invention forms a terminal electrode with small stray capacitance and sufficient strength.
本発明は、端面の一部に焼成と同時に電極を形
成することによつて、上記の課題を解決するもの
である。
The present invention solves the above problems by forming an electrode on a part of the end face at the same time as firing.
すなわち、磁性体層間を接続されて周回する導
体パターンを形成し、該導体パターンの両端を磁
性体端面に引き出し、該磁性体端面に端子電極を
形成する積層インダクタの製造方法において、該
磁性体端面の一部に該導体パターンに接続する端
子電極形成用導体ペーストを塗布し、該磁性体お
よび内部の導体パターンの焼成と同時に、端子電
極の焼付を行うことに特徴を有するものである。 That is, in a method for manufacturing a laminated inductor in which a conductor pattern is formed that connects and circulates between magnetic layers, both ends of the conductor pattern are drawn out to an end surface of the magnetic material, and terminal electrodes are formed on the end surface of the magnetic material, the end surface of the magnetic material is A conductor paste for forming a terminal electrode connected to the conductor pattern is applied to a part of the conductor pattern, and the terminal electrode is baked at the same time as the magnetic body and the internal conductor pattern are baked.
以下、図面を参照して、本発明の実施例につい
て説明する。
Embodiments of the present invention will be described below with reference to the drawings.
第1図は、本発明によつて製造される積層イン
ダクタの一例の斜視図である。フエライトの磁性
体ペーストと銀(または銀−パラジウム)の導体
ペーストを交互に印刷したものである。導体パタ
ーンを約半ターンずつ、磁性体ペースト上に端部
を接続しながら印刷し、層間から層間へ周回する
コイルパターンを内部に具えている。 FIG. 1 is a perspective view of an example of a laminated inductor manufactured according to the present invention. A ferrite magnetic paste and a silver (or silver-palladium) conductive paste are printed alternately. A conductor pattern is printed approximately half a turn at a time on the magnetic paste, with the ends connected, and a coil pattern that goes around from layer to layer is provided inside.
印刷によつて所定の層数の積層を行つた後、分
割されて一個のチツプとされる。通常、この状態
で焼成されるが、本発明においては、磁性体10
の導体パターンが露出する端面に導体ペースト1
2を塗布してから焼成する。この端子電極を形成
する導体ペーストは内部電極のペーストと異な
り、ガラスフリツトまたは磁性体フエライトと同
じ成分を混合しておくと、焼成時に、より密着し
た電極が形成される。 After a predetermined number of layers are laminated by printing, they are divided into one chip. Usually, the magnetic material 10 is fired in this state, but in the present invention, the magnetic material 10
Apply conductor paste 1 to the end surface where the conductor pattern is exposed.
2 and then bake. The conductor paste that forms this terminal electrode is different from the paste for the internal electrodes, and if the same components as the glass frit or magnetic ferrite are mixed, an electrode that is more closely bonded will be formed during firing.
磁性体層の端面に塗布する導体ペーストの面積
はできるだけ小さくした法がよい。これによつて
対向する端子電極の浮遊容量を小さくすることが
できる。ただし、強度の面、基板実装の面などか
ら、隣接する上下面まで伸ばして形成した方がよ
い。 It is preferable to minimize the area of the conductive paste applied to the end face of the magnetic layer. This allows the stray capacitance of the opposing terminal electrodes to be reduced. However, from the viewpoint of strength, board mounting, etc., it is better to form it so that it extends to the adjacent upper and lower surfaces.
第2図は、本発明の他の実施例を示す斜視図で
対向する角の部分に端子電極22を形成したもの
である。この場合には、端子電極の間隔が最大と
なり、容量の減少という面での効果は大きい。 FIG. 2 is a perspective view showing another embodiment of the present invention, in which terminal electrodes 22 are formed at opposing corner portions. In this case, the distance between the terminal electrodes becomes maximum, and the effect of reducing capacitance is significant.
また、第3図のように、四つ角に端子電極32
を形成すると、方向性がなくなり、製造面、実装
面で有利である。 In addition, as shown in FIG. 3, there are terminal electrodes 32 at the four corners.
When formed, there is no directionality, which is advantageous in terms of manufacturing and mounting.
本発明によれば、端子電極の面積が小さく、電
極間の浮遊容量を小さくすることができるので、
積層インダクタの自己共振周波数などの特性を改
善することができる。
According to the present invention, since the area of the terminal electrode is small and the stray capacitance between the electrodes can be reduced,
Characteristics such as the self-resonant frequency of the laminated inductor can be improved.
また、焼成と同時に端子電極を形成するので、
密着強度を上げることができる。そして、ガラス
フリツト等の結合材によつてよりその効果を高め
ることができる。 In addition, since the terminal electrodes are formed at the same time as firing,
Adhesion strength can be increased. The effect can be further enhanced by using a bonding material such as glass frit.
更に、焼成と焼付が同時にできるので製造工数
を大幅に低減することができる。 Furthermore, since firing and baking can be performed at the same time, the number of manufacturing steps can be significantly reduced.
第1図から第3図までは本発明の実施例を示す
斜視図、第4図は従来の積層インダクタの斜視図
を示す。
12,22,32……端子電極。
1 to 3 are perspective views showing embodiments of the present invention, and FIG. 4 is a perspective view of a conventional laminated inductor. 12, 22, 32...terminal electrode.
Claims (1)
ターンを形成し、該導体パターンの両端を磁性体
端面に引き出し、該磁性体端面に端子電極を形成
する積層インダクタの製造方法において、該磁性
体端面の一部に該導体パターンに接続する端子電
極形成用導体ペーストを塗布し、該磁性体および
内部の導体パターンの焼成と同時に、端子電極の
焼付を行うことを特徴とする積層インダクタの製
造方法。 2 該端子電極形成用導体ペーストはガラスフリ
ツトを含む請求項第1項記載の積層インダクタの
製造方法。 3 該端子電極形成用導体ペーストは該磁性体と
同じフエライトを含む請求項第1項記載の積層イ
ンダクタの製造方法。[Scope of Claims] 1. A method for manufacturing a laminated inductor, which comprises forming a conductor pattern that circulates while being connected between magnetic layers, drawing out both ends of the conductor pattern to an end surface of the magnetic material, and forming terminal electrodes on the end surface of the magnetic material. , a laminated layer characterized in that a conductor paste for forming a terminal electrode connected to the conductor pattern is applied to a part of the end face of the magnetic body, and the terminal electrode is baked at the same time as the magnetic body and the internal conductor pattern are fired. How to manufacture an inductor. 2. The method of manufacturing a laminated inductor according to claim 1, wherein the conductive paste for forming terminal electrodes contains glass frit. 3. The method of manufacturing a multilayer inductor according to claim 1, wherein the terminal electrode forming conductor paste contains the same ferrite as the magnetic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10977989A JPH02288317A (en) | 1989-04-28 | 1989-04-28 | Manufacture of laminated inductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10977989A JPH02288317A (en) | 1989-04-28 | 1989-04-28 | Manufacture of laminated inductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02288317A JPH02288317A (en) | 1990-11-28 |
| JPH0572087B2 true JPH0572087B2 (en) | 1993-10-08 |
Family
ID=14519014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10977989A Granted JPH02288317A (en) | 1989-04-28 | 1989-04-28 | Manufacture of laminated inductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02288317A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2607248Y2 (en) * | 1992-02-27 | 2001-05-28 | 太陽誘電株式会社 | Multilayer chip inductor |
| JPH0623217U (en) * | 1992-08-24 | 1994-03-25 | 太陽誘電株式会社 | Multilayer ceramic inductor |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54140959A (en) * | 1978-04-25 | 1979-11-01 | Nippon Electric Co | Method of producing laminated ceramic capacitor |
| JPS54140957A (en) * | 1978-04-25 | 1979-11-01 | Nippon Electric Co | Method of producing ceramic capacitor |
| JPS54140958A (en) * | 1978-04-25 | 1979-11-01 | Nippon Electric Co | Method of producing laminated ceramic capacitor |
| JPS57173919A (en) * | 1981-04-21 | 1982-10-26 | Tdk Corp | Laminated transformer |
| JPS5944002U (en) * | 1982-09-14 | 1984-03-23 | ティーディーケイ株式会社 | laminated transformer |
| JPS6047411A (en) * | 1983-08-25 | 1985-03-14 | 東光株式会社 | Method of forming electrode of laminar ceramic electronic part |
| JPS61100414A (en) * | 1984-10-22 | 1986-05-19 | 住友金属工業株式会社 | Feeder for ingot member |
| JPS6421609A (en) * | 1987-07-17 | 1989-01-25 | Mitsubishi Electric Corp | Dead zone corrector for electric working equipment |
-
1989
- 1989-04-28 JP JP10977989A patent/JPH02288317A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02288317A (en) | 1990-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6871391B2 (en) | Method of manufacturing laminated ceramic electronic component and laminated ceramic electronic component | |
| JP2003017327A (en) | Multilayer inductor | |
| JP2002270428A (en) | Multilayer chip inductor | |
| JP3201309B2 (en) | Laminated coil and method of manufacturing the same | |
| JP2002093623A (en) | Multilayer inductor | |
| JP2000252131A (en) | Laminated chip component | |
| JPH0210598B2 (en) | ||
| JP2002343649A (en) | Laminated ceramic chip component | |
| JPH03219605A (en) | Laminated-type inductance element | |
| JPH0645307U (en) | Multilayer chip inductor | |
| JP2002064016A (en) | Multilayer inductor | |
| JP2001102218A (en) | Multilayer chip inductor and method for production thereof | |
| JPH0572087B2 (en) | ||
| JPS6228891B2 (en) | ||
| JPH0115159Y2 (en) | ||
| JP3208842B2 (en) | LC composite electronic components | |
| JP2000269078A (en) | Laminated electronic component | |
| JPS6031242Y2 (en) | LC composite parts | |
| JP2000223315A (en) | Multilayer chip coil components | |
| JPH0447950Y2 (en) | ||
| JPH0328589Y2 (en) | ||
| JP3245835B2 (en) | Manufacturing method of multilayer inductor | |
| JPH08139547A (en) | Laminated emi filter | |
| JPH0134432Y2 (en) | ||
| JPH041704Y2 (en) |