JPH0572135B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL-controlled local oscillation circuit used in a wireless communication device.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional PLL local oscillator circuit used in a wireless communication device. The PLL oscillation circuit shown within the chain line in the figure is composed of a voltage-controlled oscillator VCO, a programmable frequency divider PD, a phase detector φD, and a low-pass filter LPF.

Programmable frequency divider to determine oscillation frequency
Initially, PD is an input terminal (multiple) for frequency division ratio data.
I was inputting the frequency setting BCD code from an external pulse counter or digital switch, but
In order to save on the number of terminals, recent IC products often have internal counters and shift registers, and input frequency data serially.

The phase detector φD compares the phase of the reference frequency _R and the output frequency of the programmable frequency divider PD,
Since a pulse with a polarity and time width corresponding to the phase difference is output from the phase detector φD, the oscillation frequency is stabilized by controlling the oscillation frequency of the voltage controlled oscillator VCO using the DC voltage integrated through the low-pass filter LPF ₁ . However, when the oscillation frequency is changed, the division ratio of the programmable frequency divider PD is changed, and in the process of applying the phase difference output of the phase detector φD to the voltage controlled oscillator VCO through the low-pass filter LPF ₁ , the low-pass filter Since there is a delay in operation due to the time constant of LPF ₁ , it takes some time for the oscillation frequency of the voltage controlled oscillator VCO to be phase locked and stabilized. This is called lock-up time, and since it is important to remove ripples contained in the frequency control voltage of the voltage controlled oscillator VCO for the local oscillator of a radio, the time constant of the low-pass filter LPF ₁ is set to a large value. As shown in FIG. 4a, the lockup time also tends to become long. Furthermore, during this period, the oscillation frequency is unstable and fluctuates, resulting in inconveniences such as radio waves with unnecessary frequencies being emitted for a short period of time, or radio waves other than the set ones being received. Although there are measures such as reducing the time constant of the low-pass filter LPF ₁ only when changing the frequency, the lock system becomes oscillatory, and there is a concern that the side effect of increasing the frequency fluctuation range as shown in FIG. 4b is possible.

Therefore, in many communication devices, local oscillator operation is stopped during the lockup period to eliminate unnecessary transmission and reception, but due to the principle of PLL, it is not possible to stop the voltage controlled oscillator VCO, so the voltage controlled oscillator
Normally, the operation of the buffer amplifier BA provided at the output section of the VCO is stopped to prevent signal injection into the mixer MIX of the signal circuit. For that, phase detector φD
A DC output voltage is used, which is obtained by integrating the unlock signal that is output when the device is out of phase through a low-pass filter LPF ₂ .

When the PLL system is locked, the unlock signal is the fifth
Since only extremely thin pulses are output as shown in Figure a, the integrated output is almost zero.

When unlocked, an output with a width according to the phase difference is generated as shown in b, so the output of the low-pass filter LPF ₂ that integrates this becomes as shown in c, and the operation of the buffer amplifier BA stops from t _O when lock loss is detected. Time to t _S exceeding threshold level
Since the buffer amplifier BA is operating during _tD , unnecessary transmission and reception is inevitable.

[Problem to be solved by the invention]

As mentioned above, the object is to completely prevent unnecessary transmission and reception when changing the frequency, and to be able to arbitrarily set the local oscillation injection stop time when changing the frequency depending on the use of the applicable radio equipment.

[Means to solve the problem]

The configuration and operation of the present invention for solving the problems mentioned in the previous section will be explained with reference to FIG.

In FIG. 1, 1 is a PLL oscillation circuit that forms the local oscillator of the radio, and in the figure, it includes a voltage controlled oscillator VCO 11, a programmable frequency divider 12,
Although a basic direct frequency division method is shown, which includes a phase detector 13 and a low-pass filter LPF 14, a mixer method may also be used. The format of the reference frequency 2 is also arbitrary.

The division ratio of the programmable frequency divider 12 is set according to the configuration of recent PLL oscillator ICs.
CK, frequency data D, latch enable signal LE
This is performed by the frequency controller 3 and is supplied by the frequency controller 3.

The oscillation output stop signal generation circuit 4, which is important in the configuration of the present invention, counts the unlock signal UL output from the phase detector 13 by an arbitrary set number of pulses, and outputs the oscillation output stop signal Q _o during that period, and oscillates. The output stop signal _Qo stops the operation of the buffer amplifier 5 and stops the output of the PLL oscillation circuit 1 from being injected into the signal mixer 6.

The operation of the oscillation output stop signal generating circuit 4 is performed by simultaneously applying a latch enable signal LE for commanding frequency change to the programmable frequency divider 12 from the frequency controller to start counting the unlock signal UL. This relationship is shown in the timing chart of FIG. The figure shows the waveforms of the unlock signal UL, the latch enable signal LE, and the oscillation output stop signal Q _o from the top.
3 outputs an extremely thin pulse even during the lock period, but the oscillation output stop signal stop circuit 4 does not count this. When the latch enable signal LE is applied, the unlock signal UL becomes the latch enable signal LE.
The oscillation output stop signal circuit 4 starts measuring the unlock signal UL at the same time or a little later.
It stops after a preset count, but during that period it outputs the oscillation stop signal _Qo . By setting the counting period to be longer than the expected maximum unlocking period, unnecessary transmission and reception can be completely prevented while the PLL oscillation circuit 1 is unlocked.

〔Example〕

The implementation circuit itself is the same as that shown in FIG.

PLL oscillation circuit 1 uses Sony CX-7925B type IC.
are using. In FIG. 6, only directly related terminals among the 14P terminals are labeled and explained.

is the clock input, is the latch enable input, and is the data input, which is a serial input provided by a 4/8-bit MCU. is the unlock signal output, and this IC includes a reference oscillator, but does not include the voltage controlled oscillator VCO, so the voltage controlled oscillator
Put the VCO output into 13, more voltage controlled oscillator
This structure outputs a VCO control signal.

Oscillation output stop signal generation circuit 4 is manufactured by Toshiba.
I am using TC4024BP binary counter. FIG. 6 shows the connection relationship between the terminals and the CX7925B.

is a clock input terminal, is a clear input terminal, and Q ₁ to Q ₇ are count output terminals.

OR the unlock signal UL from the unlock signal output terminal of the CX7925B to the clock input terminal.
It is supplied as a clock signal through the gate, and when the latch enable LE is added to the TC4024BP, it starts counting and outputs the oscillation output stop signal _Qo .
Counting output terminals Q ₁ to Q ₇ according to the desired counting period
When the output of is selected and connected to the OR gate, the signal output stop signal Q _o changes from L to H, so the buffer amplifier 5 of the PLL oscillation circuit 1 is stopped when the count output stop signal Q _o is in the L state. Through this, the intended purpose is achieved.

The operational relationship is shown in the timing chart of FIG.

In this invention, as a method of stopping the oscillation output during the unlock period of the oscillation frequency that occurs when changing the frequency of the PLL oscillation circuit 1, as shown in FIG.
The LE is used to count the required number of unlock signal outputs UL, and the oscillation output is stopped during that period.In serial transmission, the frequency setting data is sent to the data holding circuit in synchronization with the clock.
Finally, the latch enable signal LE is input to update the division ratio of the programmable frequency divider and shift to a new frequency, so in this method, the oscillation output is stopped by the latch enable signal LE,
As shown in the figure, it is possible to start stopping oscillation without too much or too little.

〔Effect of the invention〕

In order to stop the oscillation output when the frequency is changed in the PLL local oscillation circuit according to the present invention, an oscillation output stop circuit using a counter is provided, and the output of the oscillation output stop signal is started with a latch enable signal, and the unlock signal is output a predetermined number of times. By outputting an oscillation output stop signal during the measurement period, the oscillation output can be completely stopped in the unlocked state, so compared to the conventional analog method that obtains the control voltage by integrating the unlock signal, it is possible to count only the set number of unlock signals. Since it is a digital system, it has the advantage of more accurate operation compared to being affected by level differences in the unlock signal UL, variations in the constants of the integrating circuit, and temperature.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of the present invention, FIG. 2 is an operation timing chart of the oscillation stop signal generation circuit of the present invention, and FIG. 3 is a configuration diagram of a conventional PLL local oscillator and an oscillation output stop circuit when unlocked. Fig. 4 is an example of frequency transition characteristics when frequency is changed in the circuit of Fig. 3, Fig. 5 is an example of operating waveforms of the oscillation output stop circuit of Fig. 3, Fig. 6 is an implementation circuit diagram of the present invention, and Fig. 7 is the timing chart in FIG. 1...PLL oscillation circuit, 2...Reference oscillator, 3
...Frequency controller, 4...Oscillation output stop signal generation circuit, 5...Buffer amplifier, 6...Signal mixer, 12...Programmable frequency divider, 13...
...Phase detector, 14...LPF.

Claims (1)

[Claims] 1. In a PLL local oscillation circuit of a wireless communication device consisting of a voltage controlled oscillator, a programmable frequency divider, a reference frequency oscillator, a phase comparator, and an LPF, frequency division ratio data is set in the programmable frequency divider. Start counting with the latch enable signal,
An oscillation output stop signal generation circuit using a counter that inputs the unlock signal pulse of the phase comparator, counts until a predetermined value is reached, and outputs an oscillation output stop signal from the start of counting to the end of counting is provided, and the oscillation output stop signal generation circuit is provided. A PLL local oscillation circuit characterized in that the output of the voltage controlled oscillator is cut off by an output stop signal.