JPH0574229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a large-scale integrated circuit, and particularly to the structure of a highly integrated semiconductor memory device having a well for preventing soft errors.

(b) Background of the Technology In highly integrated semiconductor memory devices, stored information is lost due to alpha rays coming from the outside or alpha rays emitted from trace amounts of radioactive elements contained in packages or wiring materials. So-called soft errors are becoming an obstacle.

In particular, MOS type dynamic random access memories are susceptible to alpha rays, and therefore memory cell arrays are formed in highly doped wells having the same conductivity type as the semiconductor substrate.

FIG. 1 shows a circuit diagram of a one-transistor, one-capacitor memory cell. In the figure, transistor Q represents a transfer gate MOS-FET (field effect transistor), capacitor C represents a charge storage capacity for storing information, WL represents a word line, and BL represents a bit line.

In the figure, Vss (0V) or power supply voltage Vcc (5V) is applied to BL, and the threshold voltage of the FET is
If Vth, a voltage higher than Vcc+Vth is required for WL. As the concentration of the semiconductor substrate directly under the gate increases, Vth increases, making it difficult to drive the WL.

When the impurity concentration of the semiconductor substrate is low, the width of the depletion layer created in the memory cell is large, and among the electron-hole pairs generated when α rays are incident here, electrons are drawn into the memory cell. The holes are then pumped out of the memory cell (in the case of commonly used n-channel MOS-FETs). The electrons drawn into the memory cell lower the voltage applied between the electrodes of the charge storage capacitor, destroying the "1" level corresponding to the state in which charges are stored.
Therefore, the influence of alpha rays is reduced by increasing the impurity concentration in the memory cell area and making the depletion layer thinner.

Generally, field oxide regions and channel cut regions are used to isolate MOS elements including the MOS-FETs and the like that constitute an integrated circuit, and both are provided between adjacent elements. Since a conductive film is formed between the source or drain regions of two adjacent elements closer to the isolation part and the oxide film covering the isolation part, a parasitic MOS element is formed in the isolation part. The field oxide region thickens the gate oxide film of the parasitic element and increases its threshold voltage to prevent conduction in the isolation portion. In addition, since the channel cut region is formed by doping heavily with impurities of the same type as the semiconductor substrate, it prevents the formation of channels under the gate oxide film of parasitic elements.
Therefore, conduction in the separation section is prevented.

(c) Conventional technology and problems As semiconductor memory devices become more highly integrated, transfer gate MOS-FETs that constitute memory cells
The channel width W of is extremely narrow, less than 2μm,
Impurities are introduced into the FET gate region to form channel cut regions for isolation between elements.
This causes a so-called narrow channel effect in which the threshold voltage of the FET increases.

FIG. 2 is a plan view and a cross-sectional view taken along line AB of a conventional example of a memory cell of a highly integrated semiconductor memory device. 21 is a semiconductor substrate, 22 is a well, 23 is a channel cut region, 24 is a field oxide region, 25 is a gate oxide film, 26 is a word line forming the gate of the FET, and 27 is a counter electrode of the charge storage capacitor C. . In the figure, S represents the source, D represents the drain, and W represents the channel width.

As the semiconductor substrate 21, the impurity concentration is 1×10 ¹⁵ cm ^-3
The p ^- type silicon substrate is used, and the thickness of the memory cell area is
A well 22 with a diameter of 1 μm and an impurity concentration of 5×10 ¹⁵ cm ⁻³ is formed.

Next, with the oxidation-resistant film pattern used as a field oxidation mask formed, ion implantation for channel cutting is performed using this as an implantation mask. After this, a heat treatment process of field oxidation is performed, and the final thickness is 4000 Å and the impurity concentration is 1×.
A channel cut area 23 of 10 ¹⁶ cm ^-3 is formed. When the channel width is narrow, the impurity introduced to form the channel cut region 23 spreads laterally from left to right and overlaps as shown by the dotted line, resulting in a synthesized impurity introduced region shown by the solid line. ing.

Next, a field oxide region 24 with a thickness of 3000 Å is formed.

Next, a gate oxide film 25 with a thickness of 400 Å and a word line (gate) 26 made of a polycrystalline silicon layer with a thickness of 3000 Å are sequentially deposited on the semiconductor substrate.
Perform patterning in step 6.

In addition to the narrow channel effect, forming memory cells in highly doped wells in this way
Furthermore, the threshold voltage is increased. For this reason, the concentration of the well could not be made very high, and therefore, measures against soft errors were not sufficient.

(d) Purpose of the Invention The purpose of the present invention is to provide a semiconductor memory device that eliminates the above-mentioned drawbacks of the prior art, completely isolates elements within a memory cell, and is highly effective against soft errors. It is in.

(e) Structure of the Invention The above object is to provide a well formed in a semiconductor substrate and having an impurity concentration higher than that of the substrate, a plurality of memory cells arranged in the well, and a memory cell outside the well. MOS-FET formed on the substrate
and a peripheral circuit configured by the memory cell, each memory cell including a capacitor and a peripheral circuit configured by the peripheral circuit.
a transfer gate MOS-FET having a channel width narrower than that of the MOS-FET, isolation between the elements of the memory cell is performed by a field insulating film provided in the well, and the peripheral circuit The object of the present invention is to provide a semiconductor memory device in which element isolation is performed by a field insulating film and a channel cut region formed only outside the well.

In the present invention, the memory cell in the well
No channel cut regions are formed in the array. Since the concentration of the well is sufficiently high that the well itself acts as a channel cut, only the field oxide region is sufficient for isolation between devices. Also, since the voltage applied to the electrode of the charge storage capacitor of the memory cell connected to the bit line is at most Vcc, the memory
It does not need to be highly concentrated unlike the usual channel cut region of MOS-FETs other than cells. Therefore, since the narrow channel effect described above does not occur, the well concentration can be increased and soft error countermeasures can be ensured.

(f) Embodiment of the invention FIG. 3 is a plan view of a semiconductor substrate showing an embodiment of the invention. In the figure, 31 is a semiconductor chip;
2 is a memory cell array, 33 is a well, 34
indicates the peripheral circuit section.

The peripheral circuit section 34 includes an address buffer, an input/output control circuit, a word line drive circuit, a sense amplifier, various clock signal generation circuits, and the like.

FIG. 4 is a plan view of a semiconductor substrate showing the example in the order of steps. In the figure, 41 is a semiconductor substrate, 42
43 is a resist, 43 is a well, 44 is a silicon dioxide film, 45 is a silicon nitride film, 46 is a resist, 47 is a channel cut region, 48 is a field oxide region, 49 is a gate oxide film, and 50 is a gate. The figure shows a peripheral circuit section on the left side and a memory cell section on the right side on the same semiconductor substrate.

In FIG. 4a, a silicon substrate with an impurity concentration of 1×10 ¹⁵ cm ^-3 p ^- type is used as a semiconductor substrate 41, and a resist 42 is deposited on the peripheral circuit portion of the substrate, and this is used as a mask to attach the semiconductor substrate. Boron ions B ⁺ are implanted to form a well 43 with a thickness of 1 μm and an impurity concentration of 1×10 ¹⁶ cm ^-3 in the memory cell portion.

In FIG. 4b, the resist 42 is removed and a silicon dioxide film 4 with a thickness of 500 Å is sequentially deposited on the semiconductor substrate.
4. A silicon nitride film 45 with a thickness of 2000 Å is deposited, and this film is left on the element formation portion by a normal lithography process.

In FIG. 4c, the memory cell portion is covered with a resist 46, and using this and the pattern of the silicon nitride film 45 as a mask, boron ions are applied to the semiconductor substrate.
A channel ^cut region 47 with a thickness of 1 μm and an impurity concentration of 1×10 ¹⁶ cm ^-3 is implanted into the peripheral circuit area.
form.

In FIG. 4d, resist 46 is removed to expose the silicon substrate and a 3000 Å thick field oxide region 48 is formed in both the periphery and memory cell areas. In this case, the channel width is 6 to 6 at the periphery.
100μm, less than 2μm in the memory cell part. The figure shows a state in which the silicon dioxide film 44 and silicon nitride film 45 remaining on the element formation area have been removed after field oxidation.

In FIG. 4e, a gate oxide film 49 with a thickness of 400 Å is sequentially formed on the surface of the element forming part of the semiconductor substrate.
A 3000 Å polycrystalline silicon layer 50 for the gate is deposited and patterned into the shape of the gate electrode.

This completes the main steps according to the present invention, and the semiconductor memory device is then completed by normal steps.

(g) Effects of the Invention As described in detail above, according to the present invention, it is possible to provide a semiconductor memory device that completely isolates elements within a memory cell and is highly effective against soft errors.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a memory cell with one transistor and one capacitor, and Fig. 2 is a plan view and A-B showing a conventional example of a memory cell of a highly integrated semiconductor memory device.
FIG. 3 is a plan view of a semiconductor substrate showing an embodiment of the present invention, and FIG. 4 is a plan view of a semiconductor substrate showing the embodiment in the order of steps. In the figure, 21 is a semiconductor substrate, 22 is a well,
23 is a channel cut region, 24 is a field oxide region, 25 is a gate oxide film, 26 is a word line, 27 is a counter electrode of a charge storage capacitor, 31 is a semiconductor chip, 32 is a memory cell array, 33 is a well, 34 is a peripheral circuit section, 41 is a semiconductor substrate,
42 is a resist, 43 is a well, 44 is a silicon dioxide film, 45 is a silicon nitride film, 46 is a resist, 47
48 is a channel cut region, 48 is a field oxide region, 49 is a gate oxide film, and 50 is a gate.

Claims (1)

[Scope of Claims] 1. A well formed in a semiconductor substrate and having an impurity concentration higher than that of the substrate, a plurality of memory cells arranged and formed in the well, and a well formed in the substrate outside the well. MOS-FETs each having a capacitor and a transfer gate MOS-FET having a channel width narrower than the channel width of the MOS-FET of the peripheral circuit.
FET, isolation between elements of the memory cell is performed by a field insulating film provided in the well, and isolation between elements of the peripheral circuit is performed by a field insulating film and a channel formed only outside the well. A semiconductor memory device characterized in that processing is performed in a cut region.