JPH0574863B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention prioritizes unreported execution completion statuses corresponding to input/output commands issued from a host device through a path to an input/output device, starting from a path with a long waiting time. It relates to an input/output control device for processing.

As the usage of information processing systems has become more sophisticated and complex, the processing efficiency and operating efficiency of system control have become more demanding.

For example, multiple (e.g., 4 or 6) central processing units (hereinafter referred to as CPUs) control input/output devices (e.g., storage devices such as magnetic tape devices).
System configurations in which control is performed from become.

Generally, a plurality of input/output devices (hereinafter referred to as IOD) are connected under an input/output control device (hereinafter referred to as IOC). In addition, the IOC has a CPU-compatible path that exchanges control signals and data with the CPU, and control commands for the IOD and command completion reports (also called final status reports) for the control commands are performed through this path. .

Also, since instructions from multiple CPUs are issued asynchronously, the IOC controls these multiple instructions and
will be executed. For example, when input/output commands to multiple IODs are issued from multiple paths, each IOD reports the execution command completion, that is, the final status report, through the path that received the command. In order to do so, it is necessary to efficiently control such final status reporting.

[Problems to be solved by conventional technology and invention]

FIG. 2 shows an input/output control system diagram.

The system shown in Figure 2 is IOD3 under IOC1.
(0)~IOD3(n) to 4 CPU2(0)~
It is controlled through paths 0 to 3 from the CPU 2 (3).

For example, from CPU2 (0) through path 0
Assume that an input/output command is issued to IOD3(0). Note that the input/output command referred to here means a detachment command. Also, the detachment command is IOD3
This is a command in which the IOC1 reports the final status via paths 0 to 3 in response to an interrupt from (0) to IOD3(n), and for example, a rewind operation is the target of this command.

CPU2 (0) passes the time from when an input/output instruction is issued until the final status is reported.
Monitor by software in ~3 units. or,
The IOC 1 receives similar input/output commands, write/read commands, etc. from other paths 1 to 3, and performs control according to the commands.

On the other hand, the instructions issued by CPU2(0) to CPU2(3) have processing priority depending on the degree of urgency. command)
The final status report for is of lower priority.

Therefore, for example, under the control of the control unit 4 in the IOC 1, a timeout may occur while another command with a higher priority is being processed and the final status report is being made, and the final status report cannot be made and the IOC 1
Something that is recognized as a failure occurs.

In particular, since the final status report is processed arbitrarily, the path 0 to
There is a problem in that paths 0 to 3, which have been kept waiting for a long time, are kept waiting forever and may eventually time out and be aborted.

[Means for solving problems]

The purpose of the present invention is to realize a new input/output control device that solves the above-mentioned problems. and information indicating the path through which the input/output instruction was received, in the order of the time of the instruction, and when reporting the execution completion status for the input/output instruction, the time stored in the storage means is provided. The problem is solved by the input/output control device according to the present invention, which in turn reports the execution completion status with an interrupt.

[Operation] In other words, so that the time order in which input/output commands were instructed for each path can be identified for each path, priority is given to the path that has been waiting the longest among paths that have not yet reported the final status for the input/output command. By assigning a priority order and controlling the final status to be reported based on the priority order, paths with a long waiting time are prevented from timing out.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 shows a block diagram of an embodiment of an input/output control device according to the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Next, the operation of this embodiment will be explained. In this embodiment, it is assumed that a subsystem having four paths 0 to 3 as shown in FIG. 2 is configured.

When IOC1 receives an input/output command (disconnection command) through each path 0 to 3, the current path 0 to 3
and the machine numbers of IOD3(0) to 3(n) (e.g., #0 to #N) to multiplexer 8 (hereinafter referred to as
The addresses output from the MPX8 are sequentially written to and stored in the specified address of the memory circuit (RAM) 5.

The MPX8 normally outputs the output from the write counter 7 as a write address to the memory circuit 5 in sequence, and outputs it during the period when the IOC1 is in an idling state, that is, in a state not performing actual control processing, and is waiting for the next control processing operation. When receiving the idle signal IDL, the output is switched to the read counter 6 side.

That is, when the period of waiting for the next control processing operation (this period becomes the period in which the final status can be reported), the write data (numbers of paths 0 to 3 and IOD
3(0) to 3(n)) are read out sequentially. or,
The control unit 4 in the IOC 1 performs interrupt control for final status reporting according to the order read from the memory circuit (RAM) 5.

For example, if IOD3(0) of path 0 is read first, path 0 on the output side of the memory circuit (RAM) 5 will be set to "1", output sides of paths 1 to 3 will be set to "0", and then paths 0 to 3 will be set to "0". In addition to specifying the priority of 3, IOD
By reading the machine number as #0, the final status report from IOD3 (0) through path 0 is processed with the highest priority, and CPU2 (0) also recognizes that there is a final status report interrupt, giving priority to path 0. do.

In this way, the order of addresses specified by the read counter 6 becomes the priority order of the final status report, and the final status report is made in order.The counter value of the write counter 7 and the counter value of the read counter 6 are compared by the comparator circuit 9. If they match, a predetermined signal is output from the comparison circuit 9 to the control section 4, and the final status report is completed.

Further, the predetermined signal output from the comparison circuit 9 is sent to the write counter 7 and the read counter 6,
Reset each counter value.

〔Effect of the invention〕

According to the present invention as described above, by prioritizing interrupts from paths that have been waiting for a final status report for a long time, it is possible to prevent the non-reporting of a final status with a long waiting time from causing the software of the central processing unit to time out. It has the effect of saying that it can be done.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of an embodiment of an input/output control device according to the present invention, and FIG. 2 shows a diagram of an input/output control system. In the figure, 1 is IOC, 2(0) to 2(3) are
CPU, 3(0) to 3(n) are IOD, 4 is control unit,
5 is a storage circuit, 6 is a read counter, 7 is a write counter, 8 is MPX, and 9 is a comparison circuit.

Claims (1)

[Scope of Claims] 1. It has a plurality of paths for exchanging signals from a plurality of higher-level devices, receives input/output commands, etc. from the plurality of higher-level devices through the paths, and connects a plurality of connected input/output devices. In a device that controls a device and reports the execution completion status of the input/output instruction of the input/output device to the higher-level device by interrupt, when the input/output instruction is instructed to the input/output device, A storage means is provided for storing information indicating the input/output device and the path through which the input/output instruction was received in the time order of the instruction, and when reporting the execution completion state for the input/output instruction, the information is stored in the storage means. An input/output control device characterized in that the execution completion state is reported by interrupt in the order of time.