JPH0575136B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In channel control that has commands and status in main memory, if an error occurs during status storage, the bit indicating status store invalidity in the adapter status register is changed to an interrupt generation bit. This method is used to notify that the status is invalid by displaying it along with the status.

[Industrial application field]

According to the present invention, when an error occurs in the main memory store of the end status of a channel that has a command and end status for each I/O in the main memory of a data processing device, the error is detected through a control register in the channel. The present invention relates to a channel termination status notification method that enables prompt error processing by displaying a message and generating a normal interrupt.

[Conventional technology]

FIG. 9 is a diagram explaining the conventional technique. 9th
In the figure, 2 is main memory, 3 is channel, ACR
indicate adapter control registers, respectively. The I/O command execution sequence is
These include channel activation, command fetch, data transfer, status store, and interrupt processing. When the channel 3 stores status in the main memory 2, control signals, data addresses, data, etc. are sent to the main memory 2, and the main memory 2 returns a response signal in response. If the data was successfully stored, a response indicating that the data was stored successfully is returned.
If a bus error or the like is detected and the storage cannot be performed normally, a response is returned indicating that the storage could not be performed normally. Although there may be cases in which no response is returned to a store request issued by a channel, channel 3 monitors time in preparation for such a case. If the store cannot be stored normally or if there is no response, a CPU hardware abnormality interrupt will occur.

For some reason, DSW (Device Status
Word) If the store fails, channel 3 cannot notify the end of the I/O in which the error occurred. Therefore, there will be no completion notification to the software for any time after that I/O machine number.

In conventional technology, when an error occurs in the DSW store, an interrupt is not generated,
The time was monitored using software. A method of doing nothing was also adopted. Furthermore, considering it to be an error in the entire channel, set the AEFR (adapter error) bit of the status register AST in the adapter control register ACR to "1" in Figure 9 to detect the error when accessing from software. There is also a way to notify.

[Problem to be solved]

In the method of monitoring time using software, even if it is possible to know the cause of the error through channel operation, the cause of the pending interrupt cannot be released for that machine number, and the entire channel must be cleared and the cause of the error removed. You will not be able to restart unless you do the following.

On the other hand, in a case where time monitoring by software is not possible, there will be no I/O interrupt for the machine number in which the error has occurred, and it will not be possible to determine why this occurred. In the above case, some kind of abnormality is detected on the CPU side, so it becomes a hardware interrupt. However, it is not possible to correlate which I/O or channel was activated. In this way, the cause of the interrupt for a specific machine number in the channel remains, and there is a problem in that the cause cannot be proactively notified to the software.

Assuming that it is an error in the entire channel, the adapter status register ART in the adapter control register ACR in Figure 7 is
There is a method to set the AEFR bit to "1" and notify an error when accessing from software, but there was a problem in that the entire channel would become an error.

The present invention was created in view of this point, and the present invention allows the channel to perform a command fetch, data transfer, I/O command status store, etc. even if the status store ends with an error, it is the same as a normal end. It is now possible to proactively notify the software of completion using an interrupt and also notify the cause of the error, making it possible to minimize errors so that errors in a specific I/O machine number do not spread to errors in the entire channel. The purpose is to provide a channel termination status notification method.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention. The main memory 2 stores commands and termination status. A command and termination status set exists for each I/O. The end status is composed of a channel end status and an I/O end status. When central processing unit 1 starts channel 3,
Channel 3 fetches commands from main memory 2 and sends them to the appropriate I/O. If an error is detected when storing the I/O command end status and channel end status in main memory 2, the same processing as a normal interrupt is performed except for storing the cause of the error, and the interrupt is Turn on the iDSW (Invalid DSW) bit, which indicates that DSW store is invalid, along with the interrupt generation bit Aint in the adapter status register AST, which is the trigger. The software looks at the iDSW bit when an interrupt occurs and determines that it is an error. Furthermore, software interrupt response processing is performed to clear the cause of the interrupt within the channel.

In this way, when an interrupt occurs, the channel control register must be checked first.
Since it is originally necessary to check the interrupt bit, there is no need to worry about any increase in processing steps or performance deterioration, and early notification of failures is possible.

〔Example〕

FIG. 2 is a diagram showing an example of the system configuration. Second
In the figure, 1 is the central processing unit, 2 is the main memory, and 3
is a channel, 4 is a bus control section, 5 is a data transfer control section, 6 is a buffer, 7 is a microprocessor,
8 is ROM, 9 is RAM, 10 is I/O control section, 11-0 to 11-n are I/O,
ACR is the adapter control register,
AST is Adapter Status Register, iDVA
is the interrupt device address register, DVA is the device address register, AOP is the adapter operation register, iCTL0 and iCTL
1 indicates an interface control register, respectively. Adapter Status Register AST and Interrupt Device Address Register
iDVA is for command end interrupt, adapter operation register AOP and device address register DVA are for command activation, and interface control registers iCTL0 and iCTL1 are work registers.

FIG. 3 shows the I/O command execution sequence of the channel of the present invention. When a command called SDCR (Start DCR) is issued, the channel is started and the ABSY (Adaptor Busy) bit is turned on. The ABSY bit is only on during the channel startup phase. When a channel is activated, a command fetch is performed. Data transfer occurs after the command fetch. After data transfer is completed, status storage is performed. In the illustrated example, it is assumed that an error was detected during stator storage. After the status store, interrupt processing is performed. In the interrupt processing phase,
The iDSW bit (because an error was detected in the DSW store) is turned on and the AiNT (Adapter
Interruption) bit is turned on. When the AiNT bit is turned on, an interrupt is generated. When an interrupt permission is sent from central processing unit 1, AiNT
The bit is turned off and AiNP ((Adapter
Interruption Pending bit is turned on. The software of the central processing unit 1 performs a status check, i.e., an adapter status register.
Read the contents of AST, then iRCV
(Interruption Receive) command.
Upon receiving the iRCV command, the channel will
Turns off the bit, and also turns off the AiNP bit.

FIG. 4 is a diagram showing the flow of commands and status. In Figure 4, DCW is the device
Control word, CM is command, F is chain flag, chain data, etc. flag, BC
is the byte count, DA is the data address,
DCB is a device control block,
DCWA indicates the address of DCW, STATUS indicates the status, DCR#0 indicates the 0th device control register, and DCBA indicates the address of DCB. commands, flags, bytes
The count and data address make up the channel command. device control word
DCW stores channel command words, etc. Device control block DCB
The DCW address, status, remaining byte count, etc. are stored in . This status means the end status. This termination status includes the channel termination status and
It consists of the exit status of O. Device control word DCW and device control block DCB exist on main memory 2. The device control register DCR is
Exists in RAM9. Before the SDCR command is issued, the channel is notified of the DCB address, and the channel holds the notified DCB address in the device control register DCR. When an SDCR command is issued, the channel reads the device control block DCB based on the DCB address and reads the device control word DCW based on the DCW address in the device control block DCB.
channel command and holds it in the device control register DCR. In the status store phase,
The channel creates an exit status and stores it in the device control block DCB.

Figure 5 shows the adapter control register.
Adapter Status Register in ACR
FIG. 3 is a diagram showing the configuration of AST. In Figure 5,
Each bit has the following meaning.

ABSY (Adaptor Busy)...Indicates that the channel is executing a channel operation.

AiNP ((Adapter Interruption Pending)...
Indicates that it is in interrupt processing state. “0” when interrupt is canceled from software
become.

AiNT (Adaptor Interruption): A bit that causes an interrupt. When the CPU sends an interrupt enable signal, this bit becomes "0" and AiNP becomes "1".

iDSW (Invalid Device Status Word)...
When an error is detected in the DSW store, this bit is set to "1" and used to interrupt. AiNT
At the same time, set it to “1”.

FIG. 6 is a diagram showing a software interrupt procedure. As shown in Figure 3, if an error occurs when storing the completion status DSW of an I/O command to main memory, the channel stores the iDSW bit in the adapter status register AST along with the AiNT bit that caused the interrupt request. Set it to “1”.

As shown in Figure 6, the software determines whether the interrupt is a frontal interrupt or an abnormal interrupt during interrupt processing.
If there is an abnormality, check the iDSW bit of the adapter status register AST and clear the cause of the interrupt. Note that X40 means that only bit 6 of the adapter status register AST is "1" and the other bits are "0". In this case, the completion status of the I/O command can only be obtained via the adapter control register ACR, but it is possible to notify the software corresponding to the machine number where the error occurred and terminate the job. I can do it. It is also possible to perform retry processing at the I/O command level using software. FIG. 7 is a diagram for explaining an error detection method during data transfer, and FIG. 8 is a diagram for explaining error types and detection methods. In the figure, 1 is a central processing unit, 2 is a main memory, 3 is a channel, and 12 and 13 are error detection units, respectively.

When sending DSW from channel 3 to main memory 2, first put the address on the bus and then raise the address strobe AS. Address strobe AS
When the value rises, the main memory 2 takes in the address on the bus, and the error detection section 12 performs error detection (parity check). If a parity error is detected, the main memory 2 does not return a response to the channel (no response) since it is an error in the address section, and raises an abnormality interrupt to the central processing unit 1. If no error is detected, the main memory 2 returns a response (DTACK) instructing a transition to the data sequence.

The error detection unit 13 of channel 3 monitors timeouts (no response), and when a timeout is detected, turns on the AiNT and iDSW bits of the AST. When channel 3 receives a response instructing the transition to the data sequence, it puts DSW on the bus as data and raises the data strobe DS.

When data strobe DS rises, main memory 2
takes in the DSW on the bus and sends it to the error detection unit 12.
Performs error detection (parity check). If a parity error is detected, main memory 2
is an error in the data part, so as a response
Returns BERR (abnormality) and raises an abnormality interrupt to the central processing unit 1. If no error is detected, the main memory 2 returns DTACK (normal).

When channel 3 receives BERR, it sends the AST
Turn on AiNT and iDSW. When DTACK is received, it is recognized that the DSW transfer has completed normally.

〔Effect of the invention〕

Previously, when an error occurred in DSW store, an interrupt was not generated. In the present invention,
Since the notification is made using an interrupt, abnormalities can be detected earlier than when timeouts are monitored by software, and software time monitoring is not required. In addition, there was a method of interrupting the entire channel as an error (AEFR) as a prior art, but this resulted in an abnormal termination of the I/O command of the previous model number, which caused a major problem in the spread of the error. ,
It is also possible to perform degenerate operation in which only the processing of the machine number where the error occurred is disconnected, improving reliability.
In this way, it is possible to expect improvements in performance and reliability without increasing the amount of hardware or increasing the burden on the hardware. In the present invention, commands and status are
Since each unit has one, it is possible to quickly detect an abnormality in the event of a failure or error related to the main memory address or memory, or a failure or error due to noise on the system bus, and it is also possible to perform retry control. The present invention is particularly effective in systems that require high reliability.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing an example of the system configuration, Fig. 3 is a diagram showing an I/O command execution sequence, Fig. 4 is a diagram showing the flow of commands and status, and Fig. 5 is a diagram showing the flow of commands and status. Figure 6 shows the configuration of the adapter status register, Figure 6 shows the software interrupt processing, Figure 7 explains the error detection method during error transfer, and Figure 8 shows the types of errors. A diagram explaining the detection method and FIG. 9 are diagrams explaining the conventional technique. DESCRIPTION OF SYMBOLS 1... Central processing unit, 2... Main memory, 3... Channel, 4... Bus control unit, 5... Data transfer control unit, 6... Buffer, 7... Microprocessor, 8... ROM, 9...RAM, 10...I/
O control section, ACR...adapter control register, AST...adapter status register, iDVA...interrupt device address register, DVA...device address register, AOP...adapter operation register Registers, iCTL0 and iCTL1...interface control registers.

Claims (1)

[Claims] 1. I/O commands and channel and I/O command completion statuses are stored in the main memory.
After the central processing unit starts the channel, the channel fetches the command from the main memory, passes the command to the I/O, and stores the I/O termination status and channel termination status in the main memory. When these statuses cannot be stored correctly due to an error during data transfer in a channel using a data transfer method, the corresponding bits of the adapter status register in the channel are displayed together with the interrupt generation bit, and a command end interrupt is generated. channel termination status notification method.