JPH0575167B2 - - Google Patents
Info
- Publication number
- JPH0575167B2 JPH0575167B2 JP5187786A JP5187786A JPH0575167B2 JP H0575167 B2 JPH0575167 B2 JP H0575167B2 JP 5187786 A JP5187786 A JP 5187786A JP 5187786 A JP5187786 A JP 5187786A JP H0575167 B2 JPH0575167 B2 JP H0575167B2
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- groove
- semiconductor substrate
- resist film
- predetermined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 239000011521 glass Substances 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Weting (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、メサ型半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a mesa-type semiconductor device.
［従来の技術］
従来、メサ型半導体装置の製造は、次のように
行われている。先ず、第６図Ａ，Ｂに示す如く、
所定の構造の素子を形成した半導体基板１の表裏
両面にレジスト膜２を被着する。[Prior Art] Conventionally, mesa-type semiconductor devices have been manufactured as follows. First, as shown in Figure 6A and B,
A resist film 2 is deposited on both the front and back surfaces of a semiconductor substrate 1 on which elements of a predetermined structure are formed.
次に、第７図Ａに示す如く、メサ面を形成する
領域に対応した部分３が黒く不透明であり、その
他の領域４が透明のガラスマスク５を、同図Ｂに
示す如く、レジスト膜２の上方に配置する。 Next, as shown in FIG. 7A, a glass mask 5, in which a portion 3 corresponding to a region forming a mesa surface is black and opaque and the other region 4 is transparent, is attached to a resist film 2, as shown in FIG. 7B. Place it above.
次に、第８図Ａに示す如く、ガラスマスク５を
介して紫外線をレジスト膜２に選択的に照射した
後、これを現像してレジスト膜２にメサ面の形成
領域に対応した形状の開口部６を形成する。 Next, as shown in FIG. 8A, the resist film 2 is selectively irradiated with ultraviolet rays through the glass mask 5, and then developed to form an opening in the resist film 2 in a shape corresponding to the area where the mesa surface is to be formed. Section 6 is formed.
次に、第９図Ａ，Ｂに示す如く、開口部６を有
するレジスト膜２をマスクにして、半導体基板１
に選択エツチングを施し、メサ溝７を形成する。 Next, as shown in FIGS. 9A and 9B, using the resist film 2 having the opening 6 as a mask, the semiconductor substrate 1 is
Selective etching is performed to form mesa grooves 7.
然る後、第１０図Ａ，Ｂに示す如く、レジスト
膜２を除去し、メサ溝７に沿つて半導体基板１を
分割することにより、所定のメサ面を有するメサ
型半導体装置を得る。 Thereafter, as shown in FIGS. 10A and 10B, the resist film 2 is removed and the semiconductor substrate 1 is divided along the mesa grooves 7 to obtain a mesa type semiconductor device having a predetermined mesa surface.
［発明が解決しようとする問題点］
しかしながら、従来のメサ型半導体装置の製造
方法によるものでは、レジスト膜２に格子状に形
成された開口部６の開口幅が不均一である。特に
開口部６の交叉部分では開口幅が極端に大きくな
つている。このため、このような開口幅の不均一
な開口部６を有するレジスト膜２をマスクとして
メサ溝７を形成するため、メサ溝７の交叉部では
エツチング速度が大きくなり、メサ溝７の溝深さ
が不均一になる。このためメサ溝７の直下に残存
する半導体基板１の肉厚Ｗが不均一になる。その
結果、このようなメサ溝７に沿つて半導体基板１
を分割すると、半導体基板１に欠け等の損傷が発
生し、切断部の外観が不良になるだけでなく、所
定形状のメサ面を形成できない。更に、メサ面が
半導体基板１に形成したPN接合部まで達せず、
PN接合の界面がパツシベーシヨン膜で覆われな
い状態が発生し、素子の耐圧低下を引き起こす。
その結果、所定の仕様を満したメサ型半導体装置
を高い歩留りで得ることができない問題があつ
た。[Problems to be Solved by the Invention] However, in the conventional method for manufacturing a mesa-type semiconductor device, the opening widths of the openings 6 formed in a grid pattern in the resist film 2 are non-uniform. In particular, the opening width is extremely large at the intersection portion of the opening 6. Therefore, since the mesa grooves 7 are formed using the resist film 2 having such openings 6 with non-uniform opening widths as a mask, the etching rate increases at the intersections of the mesa grooves 7, and the groove depth of the mesa grooves 7 increases. The texture becomes uneven. Therefore, the thickness W of the semiconductor substrate 1 remaining directly under the mesa groove 7 becomes non-uniform. As a result, the semiconductor substrate 1 is formed along such mesa groove 7.
If the semiconductor substrate 1 is divided, damage such as chipping occurs in the semiconductor substrate 1, and not only does the appearance of the cut portion become poor, but also it is impossible to form a mesa surface of a predetermined shape. Furthermore, the mesa surface does not reach the PN junction formed on the semiconductor substrate 1,
A situation occurs in which the interface of the PN junction is not covered with the passivation film, causing a drop in the breakdown voltage of the device.
As a result, there was a problem in that it was not possible to obtain mesa-type semiconductor devices meeting predetermined specifications at a high yield.
［問題点を解決するための手段］
本発明は、一導電型の半導体基板のメサ面を形
成する側の面に所定の深さで形成された所定導電
型の不純物領域上にレジスト膜を被着する工程
と、該レジスト膜に前記メサ面を形成する領域に
対応したパターンの溝で該溝内に所定パターンの
残存部を有する溝開口部を形成する工程と、該溝
開口部を介して前記残存部を消失させる程度の選
択エツチングにより、前記不純物領域を貫挿して
前記半導体基板に達する深さのメサ溝を形成する
工程とを具備するメサ型半導体装置の製造方法で
ある。[Means for Solving the Problems] The present invention covers a resist film on an impurity region of a predetermined conductivity type formed at a predetermined depth on a side of a semiconductor substrate of one conductivity type on which a mesa surface is to be formed. forming a groove opening in the resist film with a pattern of grooves corresponding to the area where the mesa surface is to be formed, and having a remaining portion of a predetermined pattern in the groove; The method of manufacturing a mesa semiconductor device includes the step of forming a mesa groove deep enough to penetrate the impurity region and reach the semiconductor substrate by selective etching to such an extent as to eliminate the remaining portion.
［作用］
以上説明した如く、本発明に係るメサ型半導体
装置の製造方法によれば、予め半導体基板のメサ
溝を形成する領域に所定の不純物を導入し、か
つ、残存部を有するレジスト膜の溝開口部を介し
て残存部が消失する程度のエツチングにて半導体
基板内にメサ溝を形成するので、メサ溝の溝深さ
をほぼ均一なものに設定することができる。その
結果、半導体基板を割れ等の損傷の発生を防止し
て、良好な外観で分割し、耐圧の向上を図つたメ
サ型半導体装置を高歩留りで得ることができる。[Function] As explained above, according to the method for manufacturing a mesa semiconductor device according to the present invention, a predetermined impurity is introduced in advance into a region of a semiconductor substrate where a mesa groove is to be formed, and a resist film having a remaining portion is Since the mesa groove is formed in the semiconductor substrate by etching to such an extent that the remaining portion disappears through the groove opening, the depth of the mesa groove can be set to be substantially uniform. As a result, it is possible to prevent damage such as cracks from occurring in the semiconductor substrate, to divide the semiconductor substrate with good appearance, and to obtain mesa-type semiconductor devices with improved voltage resistance at a high yield.
［実施例］
以下、本発明の実施例について図面を参照して
説明する。先ず、第１図に示す如く、例えばシー
ト抵抗が55〜65Ω・cm、厚さ約410μｍのＮ型半導
体基板１０の表面側に拡散深さ（XjN）が30μの
Ｎ型不純物領域１１を形成し、裏面側に拡散深さ
（XjP）が180μｍのＰ型不純物領域１２を形成す
る。次いで、Ｎ型不純物領域１１及びＰ型不純物
領域１２の表面に所定の膜厚のレジスト膜１３を
形成する。[Examples] Examples of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, an N-type impurity region 11 with a diffusion depth (X jN ) of 30 μm is formed on the surface side of an N-type semiconductor substrate 10 with a sheet resistance of 55 to 65 Ω·cm and a thickness of about 410 μm, for example. Then, a P-type impurity region 12 having a diffusion depth (X jP ) of 180 μm is formed on the back side. Next, a resist film 13 having a predetermined thickness is formed on the surfaces of the N-type impurity region 11 and the P-type impurity region 12.
次に、第２図Ａに示す如く、半導体基板１０の
メサ面形成領域に対応した部分１４が黒色の不透
明領域であり、かつ、この不透明領域内の残存部
形成領域１５及び不透明領域を除くその他の領域
１６が透明領域となつたガラスマスク１７を同図
Ｂに示す如く、レジスト膜１３の上方に配置す
る。 Next, as shown in FIG. 2A, the portion 14 of the semiconductor substrate 10 corresponding to the mesa surface forming area is a black opaque area, and the remaining part forming area 15 within this opaque area and other areas excluding the opaque area. A glass mask 17 with a transparent region 16 is placed above the resist film 13, as shown in FIG.
次に、ガラスマスク１７をマスクにしてレジス
ト膜１３に紫外線を選択的に照射し、これを現像
して第３図Ａ，Ｂに示す如く、メサ面の形成領域
に対応した溝形状で、その溝内に残存部１８を有
する溝開口部１９をレジスト膜１３に形成する。
ここで、残存部１８の幅（X1）は例えば40μｍに
設定し、溝開口部１９の内壁面と残存部１８との
間隔（X2）を例えば80μｍに設定する。 Next, the resist film 13 is selectively irradiated with ultraviolet rays using the glass mask 17 as a mask, and developed to form a groove shape corresponding to the area where the mesa surface is to be formed, as shown in FIGS. 3A and 3B. A groove opening 19 having a remaining portion 18 within the groove is formed in the resist film 13.
Here, the width (X 1 ) of the remaining portion 18 is set to, for example, 40 μm, and the distance (X 2 ) between the inner wall surface of the groove opening 19 and the remaining portion 18 is set to, for example, 80 μm.
次に、第４図に示す如く、溝開口部１９を有す
るレジスト膜１３をマスクにして、弗酸：硝酸：
酢酸＝１：２：１の比率からなるエツチング液で
半導体基板１０に選択エツチングを約30分間施
し、Ｎ型不純物領域１１を貫挿して半導体基板１
０に達する深さ（約250μｍ）のメサ溝２０を形
成する。 Next, as shown in FIG. 4, using the resist film 13 having the groove openings 19 as a mask, hydrofluoric acid: nitric acid:
Selective etching is performed on the semiconductor substrate 10 for about 30 minutes using an etching solution having a ratio of acetic acid = 1:2:1, and the semiconductor substrate 10 is etched by penetrating the N-type impurity region 11.
A mesa groove 20 having a depth of 0 (approximately 250 μm) is formed.
然る後、このメサ溝２０に沿つて半導体基板１
０を分割し、所定のメサ面を有するメサ型半導体
装置を得る。 After that, the semiconductor substrate 1 is placed along the mesa groove 20.
0 is divided to obtain a mesa type semiconductor device having a predetermined mesa surface.
このようにして形成したメサ溝２０の深さを第
５図Ａに示す如く、メサ溝２０の内の１本の長手
方向に沿う７箇所（Ａ〜Ｇ）について調べたとこ
ろ、第５図Ｂに特性線にて示す如く、250〜
270μｍの範囲内にあつた。これに対して第６図
乃至第１０図に示す従来の方法で形成したメサ溝
７の場合の実施例のものと同様の７箇所の溝深さ
を調べたところ、第５図Ｂに特性線にて示す如
く、240〜370μｍの範囲にあつた。同図から明ら
かなように実施例によるものでは、従来のものに
比べて遥かに安定した均一な溝深さでメサ溝２０
が形成されていることが判つた。 The depth of the mesa groove 20 thus formed was investigated at seven locations (A to G) along the longitudinal direction of one of the mesa grooves 20, as shown in FIG. 5A. As shown in the characteristic line, 250~
It was within the range of 270 μm. On the other hand, when we investigated the groove depths at seven locations similar to those in the example in the case of the mesa groove 7 formed by the conventional method shown in FIGS. 6 to 10, we found that the characteristic line in FIG. As shown in , the diameter was in the range of 240 to 370 μm. As is clear from the figure, in the example, the mesa groove 20 has a much more stable and uniform groove depth than the conventional one.
was found to be formed.
このようにこのメサ型半導体装置の製造方法に
よれば、極めて均一な深さでメサ溝２０を容易に
形成できるので、割れ等の損傷や外観不良の発生
を防止して、半導体基板１０を正確に分割するこ
とができる。しかも、メサ溝２０の直下に残存す
る半導体基板１０の肉厚が所定値に正しく設定さ
れているので、耐圧の向上を図つたメサ型半導体
装置を高歩留りで得ることができる。 As described above, according to this method of manufacturing a mesa-type semiconductor device, the mesa groove 20 can be easily formed with an extremely uniform depth, thereby preventing damage such as cracks and appearance defects, and accurately forming the semiconductor substrate 10. It can be divided into. Moreover, since the thickness of the semiconductor substrate 10 remaining directly under the mesa groove 20 is correctly set to a predetermined value, a mesa-type semiconductor device with improved breakdown voltage can be obtained at a high yield.
［発明の効果］
以上説明した如く、本発明に係るメサ型半導体
装置の製造方法によれば、半導体基板の割れや外
観不良の発生を防止すると共に、耐圧の高向上を
図つたメサ型半導体装置を高歩留りで得ることが
できるものである。[Effects of the Invention] As explained above, according to the method for manufacturing a mesa-type semiconductor device according to the present invention, a mesa-type semiconductor device that prevents cracks in the semiconductor substrate and appearance defects and that has a high withstand voltage can be produced. can be obtained with high yield.
第１図乃至第４図は、本発明方法を工程順に示
す説明図、第５図は、本発明の効果を示す説明
図、第６図乃至第１０図は、従来のメサ型半導体
装置の製造方法を工程順に示す説明図である。
１０……半導体基板、１１……Ｎ型不純物領
域、１２……Ｐ型不純物領域、１３……レジスト
膜、１４……メサ面形成領域に対応した部分、１
５……残存部形成領域、１６……不透明領域を除
くその他の領域、１７……ガラスマスク、１８…
…残存部、１９……溝開口部、２０……メサ溝。
1 to 4 are explanatory diagrams showing the method of the present invention in the order of steps, FIG. 5 is an explanatory diagram showing the effects of the present invention, and FIGS. 6 to 10 are illustrations of conventional manufacturing of mesa-type semiconductor devices. It is an explanatory diagram showing a method in order of steps. 10... Semiconductor substrate, 11... N-type impurity region, 12... P-type impurity region, 13... Resist film, 14... Portion corresponding to mesa surface formation region, 1
5... Remaining portion forming area, 16... Other area except opaque area, 17... Glass mask, 18...
...Remaining part, 19... Groove opening, 20... Mesa groove.
Claims (1)
の面に所定の深さで形成された所定導電型の不純
物領域上にレジスト膜を被着する工程と、該レジ
スト膜に前記メサ面を形成する領域に対応したパ
ターンの溝で該溝内に所定パターンの残存部を有
する溝開口部を形成する工程と、該溝開口部を介
して前記残存部を消失させる程度の選択エツチン
グにより、前記不純物領域を貫挿して前記半導体
基板に達する深さのメサ溝を形成する工程とを具
備することを特徴とするメサ型半導体装置の製造
方法。1. A step of depositing a resist film on an impurity region of a predetermined conductivity type formed at a predetermined depth on the side where the mesa surface is to be formed of a semiconductor substrate of one conductivity type, and applying the mesa surface to the resist film. The step of forming a groove opening having a predetermined pattern of remaining portions in the groove with a groove pattern corresponding to the region to be formed, and selective etching to such an extent that the remaining portion is eliminated through the groove opening. A method for manufacturing a mesa-type semiconductor device, comprising the step of: forming a mesa groove deep enough to penetrate the impurity region and reach the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5187786A JPS62209829A (en) | 1986-03-10 | 1986-03-10 | Manufacture of mesa-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5187786A JPS62209829A (en) | 1986-03-10 | 1986-03-10 | Manufacture of mesa-type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62209829A JPS62209829A (en) | 1987-09-16 |
| JPH0575167B2 true JPH0575167B2 (en) | 1993-10-20 |
Family
ID=12899108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5187786A Granted JPS62209829A (en) | 1986-03-10 | 1986-03-10 | Manufacture of mesa-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62209829A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861660A (en) * | 1995-08-21 | 1999-01-19 | Stmicroelectronics, Inc. | Integrated-circuit die suitable for wafer-level testing and method for forming the same |
-
1986
- 1986-03-10 JP JP5187786A patent/JPS62209829A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62209829A (en) | 1987-09-16 |
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