JPH0575214B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for communication control, and particularly to an integrated circuit for communication control including a large-scale integrated circuit for serial data communication control.

[Conventional technology]

With the rapid development of data communication systems, such as computer communication systems and image communication systems, the integration of communication control circuits, which are essential to network systems, has progressed.
Various integrated circuits for communication control, including large-scale integrated circuits (hereinafter referred to as LSI), have been developed and put into practical use.

FIG. 4 is a block diagram of a first conventional communication control LSI.

The communication control LSI 21 shown in FIG. 4 is called a serial data communication control LSI, and normally has independent transmitting and receiving sections and is capable of full-duplex operation, but we will not explain it here. Omitted for brevity.

The communication control LSI 21 of the first conventional example includes at least an input buffer circuit 22 and a serial buffer circuit 23, and first writes transmission data 24 from the transmitting side, for example, a processor, to the input buffer circuit 22. . The transmission data 24 written to the input buffer circuit 22 is parallel transmission data, but is transferred to the serial buffer circuit 23 as conversion transmission data 25. Therefore, it is converted into serial transmission data in a format predetermined by the communication protocol (protocol) and sent as line transmission data 26.

FIG. 4 shows that the communication control LSI of the first conventional example basically only had the function of converting parallel transmission data into serial transmission data and transmitting it.

Therefore, in order to monitor transmission data errors due to an abnormality in the transmitting section of the communication control LSI, noise on the line, accidents, etc., the transmitting side must wait for a response signal from the receiving side after transmission is completed, and then I needed to check whether the data arrived correctly.

FIG. 5 is a block diagram of a second conventional communication control LSI.

This second example is a serial data communication control LSI like the first example, but the line transmission data 39 is inputted to the receiving unit 35 via the connection line 42 as the line status monitoring input signal 40. , this is transferred from the receiving section 35 to the input/output buffer circuit 32 as comparison transmission data 41, and the input/output buffer circuit 32
transfers the transmission data 36 received from the transmission side as the transmission data 37 for conversion to the input buffer circuit 39, and also feeds back the transmission data 41 for comparison to the transmission side, and the input buffer circuit 33 inputs the transmission data 37 for conversion. The serial buffer circuit 34 converts the parallel conversion transmission data 38 into serial line transmission data 39 and sends it out.

In this case, the transmission data 36 is held in advance in the memory within the system on the transmitting side.

Therefore, if the comparison transmission data 41 is fed back to the transmission side via the input/output buffer circuit 32, the transmission data can be checked by the processor on the transmission side by appropriately comparing it with the transmission data 36 held in the system memory. Errors can be monitored.

[Problem that the invention seeks to solve]

These conventional communication control LSIs mentioned above basically only have the function of converting parallel transmission data into serial transmission data and sending it out, so it is necessary to monitor the transmission data for errors as is. As shown in the first conventional communication control LSI, the transmitting side needs to wait for a response signal from the receiving side after the transmission is completed and check whether the transmitted data has arrived normally. Ta.

However, with this method, even if the transmitted data does not arrive accurately during transmission, for example due to a line malfunction, the data will continue to be sent unnecessarily, and in some cases, the data transfer efficiency will be significantly reduced. The drawback was that it deteriorated. Another disadvantage is that the transmitting side must prepare software to recognize the receiving side's response signal, and the software becomes complicated and reduces the efficiency of the entire system.

In addition, as shown in the second conventional communication control LSI, the transmission data for comparison is fed back to the transmission side system via the reception section, and the transmission data is fed back to the transmission side system memory by the transmission side processor. Even if it were possible to immediately determine errors in the transmitted data by appropriately comparing it with the transmitted data held in It had the disadvantage that it could not be used effectively because it was used for line monitoring other than its original purpose.

It is an object of the present invention to reduce the burden on the software of the transmitting system, prevent a decrease in the transmission efficiency of transmitted data and the efficiency of the entire system, and to be able to immediately determine errors in transmitted data, and to meet the purpose. An object of the present invention is to provide a communication control integrated circuit that can be used effectively.

[Means for solving problems]

The communication control integrated circuit of the present invention includes an input buffer circuit that inputs transmission data and outputs transmission data for holding and transmission data for conversion obtained by performing parallel/serial conversion of the transmission data, transmission data for comparison, and line status. a state comparison circuit that inputs and compares a monitoring input signal and outputs a mismatch display signal and a mismatch detection internal signal when the comparison transmission data and the line state monitoring input signal do not match; and the mismatch detection internal signal. a retransmission control circuit that outputs a retransmission control signal when a signal is input; and a retransmission control circuit that inputs and holds the holding transmission data, outputs the comparison transmission data, and transmits the transmission data based on the retransmission control signal. a transmission data holding circuit that outputs reconversion transmission data obtained by parallel-to-serial conversion of data; and a serial buffer circuit that inputs the conversion transmission data and the reconversion transmission data and outputs line transmission data. It consists of:

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a communication control LSI of the present invention.

This embodiment includes an input buffer circuit 2 which inputs transmission data 7 and outputs transmission data 10 for holding and transmission data 8 for conversion converted from parallel to serial, and transmission data 13 for comparison and input for line status monitoring. a state comparison circuit 6 which inputs and compares the signal 16 and outputs a mismatch display signal 15 and a mismatch detection internal signal 14 when the comparison transmission data 13 and the line state monitoring input signal 16 do not match; ,
A retransmission control circuit 5 that outputs a retransmission control signal 12 when a mismatch detection internal signal 14 is input, and a retransmission control circuit 5 that inputs and holds transmission data 10 for holding, outputs transfer data 13 for comparison, and outputs a retransmission control signal 12. A transmission data holding circuit 4 that outputs transmission data 11 for reconversion that has been subjected to parallel/serial conversion based on
, transmission data for conversion 8 and transmission data for re-conversion 1
1 and a serial buffer circuit 3 which inputs line transmission data 9 and outputs line transmission data 9.

FIG. 2 is a block diagram of a first usage example of the communication control LSI of the present invention.

In this first usage example, line transmission data 9 sent out from the communication control 1 LSI of this embodiment is inputted to the status comparison circuit 6 as the line status monitoring input signal 16 via the connection line 17, and the status is compared. The circuit 6 sends comparison transmission data 13 and line status monitoring input signal 1.
6 is compared. If the two do not match, it outputs a mismatch display signal 15 and a mismatch detection internal signal 14 to notify that there is a mismatch, and upon receiving the mismatch detection internal signal 14, the retransmission control circuit 5 outputs a retransmission control signal. 12 to the transmission data holding circuit 4, and from there transmit data 1 for reconversion.
1 is outputted to the serial buffer circuit 3 and sent out again as line transmission data 9.

In this way, in the first usage example,
The LSI 1 includes a transmission data holding function and a comparison function, which in the conventional example had to be carried out within the transmitting system, as well as a retransmission request function in the case of a mismatch.

Therefore, as shown in this first usage example, if the communication control LSI of one embodiment of the present invention is used, there will be no need to place an extra burden on the transmitting system or to reduce the communication control LSI.
It is possible to monitor transmitted data for errors without inefficient use of the LSI.

FIG. 3 is a block diagram of a second usage example of the communication control LSI of the present invention.

The second usage example is the line interface circuit 18.
a and 18b, the output of the series buffer circuit 3 and the line interface circuit 18a
from the communication line 19 connected via the connection line 2
0, the line status monitoring input signal 16 is sent to the status comparison circuit 6 via the line interface circuit 18b.
It feeds back to the input of

This example is basically the same as the first example, although line interface circuits 18a and 18b are involved.

〔Effect of the invention〕

As explained above, the present invention provides a communication control integrated circuit with a function to hold transmitted data, a function to compare it with the transmitted data on the line, and a retransmission function in the case of a mismatch, so that the software of the transmitting side system can be It also reduces the burden on the operation of the communication control integrated circuit, prevents a decrease in the transmission data transfer efficiency and the efficiency of the entire system, and makes it possible to immediately determine errors in the transmission data. The effect is that it can be used effectively to suit the purpose.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the communication control LSI of the present invention, Fig. 2 is a block diagram of a first usage example of the communication control LSI of the present invention, and Fig. 3 is a block diagram of an embodiment of the communication control LSI of the present invention. Block diagram of the second usage example of LSI, No. 4
The figure is a block diagram of a first example of a conventional communication control LSI, and FIG. 5 is a block diagram of a second example of a conventional communication control LSI. 1... Communication control LSI, 2... Input buffer circuit, 3... Series buffer circuit, 4... Transmission data holding circuit, 5... Retransmission control circuit, 6... Status comparison circuit, 7... Transmission data , 8... Transmission data for conversion, 9... Transmission data for line, 10... Transmission data for holding, 11... Transmission data for re-conversion, 12
... Re-communication control signal, 13 ... Transmission data for comparison, 14 ... Mismatch detection internal signal, 15 ... Mismatch display signal, 16 ... Line state monitoring input signal,
17...Connection line, 18a, 18b...Line interface circuit, 19...Communication line, 20...Connection line, 21...Communication control LSI, 22...Input buffer circuit, 23...Series buffer circuit, 24...
Transmission data, 25... Transmission data for conversion, 26...
...Line transmission data, 31...Communication control LSI,
32... Input/output buffer circuit, 33... Input buffer circuit, 34... Series buffer circuit, 35...
Receiving unit, 36... Transmission data, 37... Transmission data for conversion, 38... Transmission data for conversion, 39...
Transmission data for line, 40... Input signal for line status monitoring, 41... Transmission data for comparison, 42... Connection line.

Claims (1)

[Claims] 1. an input buffer circuit that inputs transmission data and outputs holding transmission data and conversion transmission data obtained by parallel-to-serial conversion of the transmission data;
A status comparison that inputs and compares transmission data for comparison and an input signal for line status monitoring, and outputs a mismatch display signal and a mismatch detection internal signal when the comparison transmission data and the line status monitoring input signal do not match. a retransmission control circuit that outputs a retransmission control signal when the mismatch detection internal signal is input; a retransmission control circuit that inputs and holds the holding transmission data; outputs the comparison transmission data; a transmission data holding circuit that outputs reconversion transmission data obtained by parallel-to-serial conversion of the transmission data based on a transmission control signal; and a transmission data holding circuit that outputs reconversion transmission data obtained by performing parallel/serial conversion of the transmission data; 1. A communication control integrated circuit comprising: a serial buffer circuit that outputs .