JPH0576175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a heterojunction transistor.

(Prior art) Conventionally, in a method for manufacturing a heterojunction bipolar transistor, three epitaxial layers, a collector, a base, and an emitter layer, are created, and
Both atypical epitaxial layers, p-type and p-type, were grown.

However, when epitaxial layers of different shapes are grown by vapor phase growth, it is generally difficult to avoid mutual contamination between impurities between the layers, and it is difficult, for example, to grow each layer at the same time in the same furnace. Therefore, the manufacturing method thereof is complicated and has the drawback of deteriorating the characteristics of the interface between each layer, thereby deteriorating the performance of the transistor.

(Object of the Invention) The present invention has been made in view of the above points, and it is a method for manufacturing a heterojunction transistor in which a high-performance heterojunction bipolar transistor can be obtained by a simple method without performing epitaxial crystal growth of an atypical type. The purpose is to provide a method.

(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows the impurity concentration distribution in the depth direction of each layer of a semiconductor heterojunction transistor. As shown in this figure, there is p-type high concentration substrate material (p ⁺ layer) at a depth of _D3 or more. On the other hand,
A _{low concentration} n-type epitaxial layer (n ₁ ^-
layer), a high concentration n-type epitaxial layer (n ⁺ layer) between D ₁ and D ₂ above it, and a low concentration n-type epitaxial layer (n ₂ ^- layer) between D ₀ and D ₁ above it. Grow in vapor phase.

When carried out in this way, since epitaxial growth is of the same type, the problem of contamination between each layer, such as the problem of compensation between different type impurities and the problem of inversion, is reduced. Crystals can be grown sequentially in the process. Therefore, the process is simplified and speeded up, and at the same time, the problem of contamination and mismatch between layers is reduced because the process is not taken out of the furnace, and it is possible to grow a high-quality interface.

FIG. 2 shows an example of the energy gap distribution in the depth direction of each layer. In this example, the substrate at a depth of _D3 or more is the layer with the smallest energy gap, and the layers have larger energy gaps as they approach the surface layer. Here, the essential requirement is that when the n ₂ ^- layer is the emitter layer, the n ⁺ layer is the base layer, and the n ₁ ^- layer is the collector layer, the emitter layer (n ₂ ^- layer) between D ₀ and D ₁ is The energy gap Eg ₁ is the base layer between D ₁ and D ₂ (n ⁺
This means making the energy gap larger than the energy gap Eg ₂ of the layer). The energy gaps Eg ₃ and Eg ₄ of the other collector layers (n ₁ ⁻ layer) and the substrate p ⁺ layer should be approximately equal to or smaller than Eg ₂ , that is, not very large.

After epitaxial growth as described above,
p so that it has an impurity concentration distribution as shown in Figure 1.
The type impurity is diffused from the surface D ₀ at a surface concentration N ₄ . The requirements for the p-type impurity concentration distribution in this case are:
The p-type concentration is large in the n ^- ₂ layer between D ₀ and D ₁ and the n ^- ₁ layer between D ₂ and D ₃ , and the p-type concentration is smaller in the n ⁺ layer between D ₁ and D ₂ . It is to be. When such diffusion is performed, a pnp type junction can be obtained in one diffusion step.

Note that this diffusion may be performed after ions are once implanted into the n ⁻ ₂ layer near the surface. Further, impurities may be introduced spatially selectively.

The transistor manufactured in this manner has a low base resistance due to the high concentration of the base layer, and high injection efficiency due to the wide gap emitter, so that a high performance transistor can be obtained at the same time.

Note that although the above method is for obtaining a pnp type transistor, an npn type transistor can also be easily obtained in the same manner. That is, n and p in the impurity concentration distribution may be replaced. Specifically, p-type epitaxial growth may be performed using an n ⁺ type substrate, and n-type impurity diffusion may be performed.

Further, although a compound semiconductor is generally used as the semiconductor material, it is not limited thereto.

Further, in the above explanation, the roles of emitter, base, and collector were given in the depth direction, but the role is not limited to this. That is, for example D ₂ ,
In order to make the space between D ₃ an emitter layer, it is sufficient to make the energy gap larger than that between the base layers D ₁ and D ₂ .
By creating an energy gap between D ₀ and D ₁ that is not larger than that between D ₁ and D ₂ in the base layer, it can be used as a collector layer. In this way, the surface becomes the collector layer, and the deep area between D ₂ and D ₃ becomes the emitter layer.

Further, since the above-mentioned elements can be selectively manufactured as a large number of transistors on the same substrate, it is needless to mention in detail that an integrated circuit can also be manufactured.

Furthermore, although FIG. 1 shows a steep change between each layer, it goes without saying that a distribution with a more gradual change may also be used.

(Effect of the invention) As detailed above, according to the method of this invention,
Since only the same type of epitaxial growth is used, there is no impurity contamination between each layer, and since each layer can be grown in one time, the quality of the interface between the layers is good. Since it is a wide gap emitter, a high performance transistor can be obtained, and it has the advantage of being a simple manufacturing method. The method of the present invention can be used not only for a single device but also as a method for manufacturing an integrated circuit.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining an embodiment of the method for manufacturing a heterojunction transistor according to the present invention. FIG. 1 is a diagram showing the impurity concentration distribution in the depth direction of each layer of the transistor, and FIG. The figure shows an example of the energy gap distribution in the depth direction of each layer of a transistor.

Claims (1)

[Claims] 1. A step of growing a heterojunction epitaxial layer having only one of n-type or p-type and including a base layer with a high impurity concentration, and adding only one of p-type or n-type to this heterojunction epitaxial layer. 1. A method for manufacturing a heterojunction transistor, comprising: forming a pnp or npn type heterojunction by diffusing impurities.