JPH0582067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MIS transistor and a method for manufacturing the same.

In order to increase the performance of MIS transistors, for example MOS transistors, it is necessary to reduce the dimensions of the MOS transistors according to the scaling law. As a result, the substrate impurity concentration increases in inverse proportion to the gate length. Furthermore, when a substrate bias is not used, it is necessary to increase the impurity concentration in inverse proportion to the square of the gate length. Furthermore, in order to prevent the characteristics of the transistor, particularly punch-through, various channel dopings are performed in the gate region.

If this is done, the impurity concentration directly under the gate insulating film will increase extremely, and for example, in a device with a gate length of about 0.3 μm, the surface impurity concentration will be about 10 ¹⁸ cm ⁻³ in total for P-type and N-type. In this situation
Carrier mobility decreases not only due to carrier scattering due to the insulator interface specific to MOS transistors, but also due to impurity scattering.

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an MIS transistor and a manufacturing method in which carrier mobility does not decrease even when the channel is shortened.

According to the first invention, the total impurity concentration in a region of the semiconductor layer in contact with the gate insulating film with a depth of 50 Å to 150 Å is 10 ¹⁵ cm ^-3 or less, and the impurity concentration in a region deeper than that and where a depletion layer occurs. But 10 ¹⁷ cm ^-3
An MIS transistor characterized by having a portion exceeding .

Further, a semiconductor single crystal layer having an impurity concentration of 10 ¹⁵ cm ^-3 or less is epitaxially grown on the semiconductor surface of the gate region according to the second aspect of the present invention, and then an oxide film is grown on the surface of this growth layer. A method for manufacturing an MIS transistor is obtained, characterized in that the remaining semiconductor layer has a thickness of 50 Å to 150 Å.

Hereinafter, the first invention will be explained in detail based on theoretical studies, taking a MOS transistor as an MIS transistor as an example. According to the scaling law, when the channel length L is reduced to 1/k, it is necessary to reduce the dimensions of other parts, such as the depth of the depletion layer under the gate x _D and the gate insulating film t _OX to 1/k. Furthermore, in order to reduce the voltage to 1/k, the threshold voltage V _T is also reduced to 1/k. Assuming that the basic device is one with zero substrate bias, such as the current MOSIC, in a device scaled down to 1/k, the depletion layer depth x _D under the gate can be reduced to ¹ /k by multiplying the substrate impurity concentration by k2. It becomes k.

In this case, the threshold voltage V _T remains constant, so in order to reduce V _T to 1/k, it is necessary to dope the gate surface with an impurity of the opposite type to that of the substrate.
Therefore, the impurity concentration k near the surface directly under the gate increases at a rate of more than ^twice . Currently, channel length is 2μm
The substrate concentration for a MOS transistor is 10 ¹⁶ cm ^-3
Therefore, in a transistor with a channel length of 0.5 μm or less, unless a region with an impurity concentration of 10 ¹⁷ cm ^{-3 or} more exists under the gate, the depletion layer width increases and the short channel effect cannot be suppressed.

These impurities, whether donors or acceptors, act as centers of ionization scattering for carriers, reducing carrier mobility, degrading transistor performance, and offsetting the high speeds obtained through miniaturization. .

An explanation will be given below using an N-channel MOS transistor as an example, but the same argument can be made for a P-channel as well.

Figure 1 is a schematic cross-sectional view of a conventional MOS transistor, where 1 is a P-type single crystal silicon substrate, 2 is an n-type diffusion layer that becomes a source, and 3 is an n-type diffusion layer that becomes a drain.
A type diffusion layer, 4 a gate insulating film, and 5 a gate electrode. Channel doping may be performed in the substrate region of the P-type substrate 1 in order to suppress the short channel effect or to adjust the threshold voltage.

FIG. 2 is a diagram showing the relationship between impurity concentration and carrier mobility, where 11 is an electron and 12 is a hole. As is clear from this figure, when the impurity concentration of either electrons or holes becomes greater than 10 ¹⁵ cm ^-3 , the carrier mobility decreases, and when it exceeds 10 ¹⁷ cm ^-3 , the value becomes less than half of that at low concentrations. I get used to it.

Figure 3 is based on the conventional method, and in order to suppress the short channel effect, the gate oxide film thickness was set to 200 Å, the depletion layer thickness was set to 800 Å, and V _T was set to 0.4 V.
Impurity distribution under the gate of MOS transistor and
FIG. 7 is a diagram showing the carrier concentration distribution when the gate bias is 5V and the transistor is in the ON state. In the figure, 21 shows the interface between the insulating film and the silicon substrate, 22 the boron distribution, 23 the arsenic distribution, 24 the inversion layer electron distribution, and 25 the depletion layer edge. This figure was obtained by computer simulation.
The carrier distribution is assumed to be a Boltzmann distribution, but since the condition is at room temperature, the effect of quantization is small, and the accuracy is sufficient to prove the effect of the present invention.

As can be seen in Figure 3, near the surface where there are many carriers, boron is 2×10 ¹⁷ cm ^-3 and arsenic is 3×
10 ¹⁷ cm ^-3 or more, resulting in a total of 5×10 ¹⁷ cm ^-3 or more. According to the relationship between the carrier mobility and the impurity concentration shown in FIG. 2, the carrier mobility in this case is about 1/3 of that in the case where there is no effect of the impurity. In reality, due to the shielding effect of impurity ions by the inversion layer carrier, the carrier mobility does not decrease that much, but in any case, the characteristics of the MOS transistor deteriorate considerably.

On the other hand, as can be seen from FIG. 3, most of the inversion layer carriers are concentrated in a region up to 50 Å from the surface. Therefore, the impurity concentration in that part was set to 10 ¹⁵ cm ^-3
It is clear that the carrier mobility will not decrease if the following conditions are used.

FIG. 4 is a schematic cross-sectional view showing the structure of an embodiment of a MOS transistor according to the first invention, in which 1 is P.
type single crystal silicon substrate, 2 an n-type diffusion layer serving as a source, 3 an n-type diffusion layer serving as a drain, 4 a gate insulating film, 5 a gate electrode, and 6 contacting the gate insulating film specially provided in the present invention. The total impurity concentration in the semiconductor layer to a depth of 50 Å to 150 Å is 10 ¹⁵ cm ^-3
The semiconductor layer has a low impurity concentration as follows.

Figure 5 shows the same depletion layer thickness as the device in Figure 3;
This shows the impurity distribution and carrier distribution for a MOS transistor with a threshold voltage of , and the impurity concentration in the region 100 Å from the surface is almost zero. 31 is the interface between the insulating film and silicon, 32
33 shows the distribution of boron, 34 shows the distribution of inversion layer electrons, and 35 shows the edge of the depletion layer.

As described above, if the thickness of the low impurity concentration layer is thin and is 150 Å or less as in the first invention, it is possible to manufacture devices with the same threshold voltage and depletion layer thickness as conventional methods using current process technology. is possible.

In the example of FIG. 5, 99.6% of the carriers are in the region with low impurity concentration, and it is clear that the current of the transistor does not decrease due to impurity scattering.
Exactly the same argument can be made for P-channel MOS transistors by changing the type of impurity.

Such a structure is also possible by combining conventional techniques. For example, by increasing the acceleration voltage during channel doping by ion implantation, which is commonly used in the manufacture of MOS devices, it is possible to create a highly concentrated layer only in the deep region under the gate, without leaving impurities near the surface. However, in this method, the shape of the impurity distribution is determined by the acceleration energy,
The degree of freedom in design is low, and the short channel effect cannot be sufficiently suppressed.

By using the MIS transistor manufacturing method of the second invention, the structure of the first invention can be easily realized, and the degree of freedom in its design is high. In this method, in the conventional MOS transistor manufacturing process, after channel doping of the gate region, the semiconductor layer in the gate region is exposed, and a thin semiconductor layer is grown in that region using molecular beam epitaxy or the like. This film thickness is the sum of the semiconductor layer thickness lost due to subsequent oxide growth on the gate and the semiconductor layer thickness required for the device structure of the present invention.

Thereafter, a gate oxide film is grown by a method such as thermal oxidation. The rest is the same as the conventional method. According to this method, if the thermal process after epitaxial growth is kept at a sufficiently low temperature, the impurity concentration in the semiconductor layer through which carriers flow can be made sufficiently low, regardless of the impurity distribution on the substrate side. This increases the degree of freedom in device design, making it possible to manufacture better devices.

Also, when this method is applied to the CMOS process,
P channel transistor and N after channel doping
The semiconductor layer can be grown simultaneously with the channel transistor, and the process does not become particularly complicated.

The present invention has the effect of providing an MIS transistor and a manufacturing method in which carrier mobility does not decrease even when the channel is shortened.

[Brief explanation of the drawing]

Figure 1 is a schematic cross-sectional diagram of a conventional N-channel MOS transistor, Figure 2 is a diagram showing the relationship between impurity concentration and carrier mobility, and Figure 3 is a diagram showing the impurity distribution and carrier distribution under the gate of a conventional transistor. Figure 4 is a schematic cross-sectional view of an embodiment of the MOS transistor of the present invention, and Figure 5 is a MOS transistor according to the present invention.
FIG. 3 is a diagram showing an example of impurity distribution and carrier distribution under the gate of a transistor. 1 is a P-type substrate, 2 is an n-type diffusion layer that becomes a source,
3 is an n-type diffusion layer serving as a drain, 4 is a gate insulating film, 5 is a gate electrode, and 6 is a low impurity concentration layer.

Claims (1)

[Claims] 1. A depth of 50 mm in the semiconductor layer in contact with the gate insulating film.
The total impurity concentration in the region from Å to 150 Å is 10 ¹⁵ cm ^-3
What is claimed is: 1. A MIS transistor characterized in that the impurity concentration in the region where a depletion layer occurs exceeds 10 ¹⁷ cm ^-3 and is deeper than that. 2 Impurity concentration on the semiconductor surface in the gate region
A semiconductor single crystal layer of 10 ¹⁵ cm ^-3 or less is epitaxially grown, and then an oxide film is grown on the surface of this grown layer, so that the thickness of the remaining semiconductor layer among the grown layers is 50 Å to 150 Å. A method for manufacturing an MIS transistor characterized by the following.