JPH0582980B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a connection structure of internal lead wires of a semiconductor device package, particularly a semiconductor device package on which an IC chip is mounted.

[Conventional technology]

Traditionally, ECL type logic ICs, especially multi-output logic ICs
The high-potential side power supply terminal in the package is used separately into the highest potential terminal (hereinafter abbreviated as V _CC terminal) and the collector terminal of the output transistor (hereinafter abbreviated as V _CCA terminal). This is to prevent V _CC from being directly affected by the noise voltage generated by the transient current flowing when the output transistor switches through the parasitic inductance of the package leads and bonding wires.

FIG. 3 shows the behavior of transient current when the ECL type logic output circuit and the output transistor as described above switch. This current generates a noise voltage due to parasitic inductance L. Especially when there are multiple outputs, a noise voltage of several hundred mV may occur at the collector terminal of the output transistor, and the V _CCA terminal is used to prevent V _CC from receiving this noise voltage directly. There is.

FIG. 2 is a diagram showing the lead connection structure of a conventionally used package. In the same figure, 1
Assume that the P terminal is the V _CCA terminal and the 2np terminal is the V _CC terminal.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional package, the V _CC terminal and
The V _CCA terminal was used as an independent pin. By the way, with the recent increase in the speed of ICs, the output rise time of the logic output of ICs has a very short and steep characteristic, and the noise voltage △ due to parasitic inductance.
V (=-L di/dt) tends to become larger and larger. Furthermore, this steep output rise characteristic causes overshoot on the output High side, which appears as output ringing or output oscillation. On the other hand, it has been found that this output ringing or oscillation can be suppressed by shorting the V _CC and V _CCA terminals near the internal pads of the IC. Therefore, the above ringing can be prevented by bonding both terminals between the internal pad of the IC and the internal lead of the package. However, in this case, the noise voltage mentioned above is directly
This will affect the V _CC pin. The input characteristics are most affected by this noise voltage, and in the worst case, there is a risk of exceeding the input characteristics standard and causing erroneous operation.

[Means for solving problems]

A semiconductor device package of the present invention is a semiconductor device package for a multi-output ECL type logic IC having a highest potential terminal, in which a terminal adjacent to the highest potential terminal and connected to the collector of an output transistor and the highest potential terminal are connected to each other. are short-circuited by an internal lead wire near the external lead terminal section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view showing one embodiment of the present invention. In the figure, package 1 is connected to IC chip 2,
It has an internal lead wire 3, an IC internal pad 4, a bonding wire 5 that connects the IC internal pad 4 and the internal lead wire 3, and further includes a terminal 1P and a terminal 2.
It is equipped with a shorting line 6 for connecting to nP. The V _CC terminal 2nP and the V _CCA terminal 1P are short-circuited by a shorting wire 6 on the internal lead wire of the package 1. In this case, output ringing can be suppressed even if there is a short circuit anywhere on this internal lead. However, since the noise voltage caused by the above-mentioned transient current is usually suppressed by a noise bypass capacitor, it is larger nearer to the internal pad 4 of the IC and smallest nearer to the external lead terminal. Therefore, by short-circuiting both terminals at the point closest to the external lead terminal, output ringing can be suppressed without deteriorating the input characteristics.

〔Effect of the invention〕

As explained above, according to the semiconductor device package of the present invention, a multi-output system having the highest potential terminal can be used.
In ECL type logic IC packages, by shorting the highest potential terminal and other terminals, that is, the collector terminal of the output transistor, with an internal lead wire close to the external lead terminal section, output ringing is suppressed and stable input characteristics are obtained. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an example of a semiconductor device package according to the present invention, FIG. 2 is a plan view showing an example of a conventional semiconductor device package, and FIG. 3 is an ECL
FIG. 2 is a circuit diagram showing an example of a type logic output circuit. 1... Semiconductor device package, 2... IC chip, 3... Internal lead wire, 4... IC internal pad,
5...Bonding wire, 6...Short wire.

Claims (1)

[Claims] 1. In a semiconductor device package for a multi-output ECL type logic IC having the highest potential terminal, the terminal adjacent to the highest potential terminal and connected to the collector of the output transistor and the highest potential terminal are located close to the external lead terminal section. A semiconductor device package characterized by short-circuiting through internal lead wires.