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JPH0584675B2 - - Google Patents
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JPH0584675B2 - - Google Patents

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Publication number
JPH0584675B2
JPH0584675B2 JP3142286A JP3142286A JPH0584675B2 JP H0584675 B2 JPH0584675 B2 JP H0584675B2 JP 3142286 A JP3142286 A JP 3142286A JP 3142286 A JP3142286 A JP 3142286A JP H0584675 B2 JPH0584675 B2 JP H0584675B2
Authority
JP
Japan
Prior art keywords
substrate
insulating substrate
semiconductor
film
stabilized zirconia
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3142286A
Other languages
Japanese (ja)
Other versions
JPS62189747A (en
Inventor
Yoshinobu Kakihara
Shuji Enomoto
Fumihiro Atsunushi
Tsukasa Doi
Toshuki Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3142286A priority Critical patent/JPS62189747A/en
Publication of JPS62189747A publication Critical patent/JPS62189747A/en
Publication of JPH0584675B2 publication Critical patent/JPH0584675B2/ja
Granted legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Inorganic Insulating Materials (AREA)

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は半導体用絶縁基板の改良に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Application> The present invention relates to improvements in insulating substrates for semiconductors.

<従来の技術> 従来よりサフアイア基板は、たとえばSOS技術
において、Si基板の代りに半導体用絶縁基板とし
て用いられている。SOS技術は、サフアイア基板
の上にSi薄膜をエピタキシヤル成長させMOSデ
バイス等を構成し、従来問題となつていた配線容
量と素子間分離とを解決し、MOSデバイス等の
高速化を図る様にしたものである。しかし、サフ
アイアを用いたSOS基板では、高温でシリコン等
の半導体をエピタキシヤル成長させると、原料ガ
スに使用している水素によつて、サフアイア基板
の母体表面の一部が還元され、サフアイア基板上
に形成したシリコンのエピタキシヤル層の中に
は、還元された金属Alもしくは酸素がドープさ
れ、汚染されていることが知られている。従つ
て、サフアイア基板上にエピタキシヤル成長した
半導体層の電気的特性や結晶性が著しく低下す
る。このため、サフアイア基板は実用基板として
の性能が阻害されていて、十分実用化されていな
いのが実情である。
<Prior Art> Sapphire substrates have conventionally been used as insulating substrates for semiconductors instead of Si substrates, for example in SOS technology. SOS technology forms MOS devices by epitaxially growing a Si thin film on a sapphire substrate, solving the conventional problems of wiring capacitance and isolation between elements, and increasing the speed of MOS devices. This is what I did. However, with SOS substrates using saphire, when semiconductors such as silicon are epitaxially grown at high temperatures, part of the base surface of the saphire substrate is reduced by the hydrogen used as the raw material gas, and the surface of the saphire substrate is reduced. It is known that some of the silicon epitaxial layers formed in 2015 are doped with reduced metal Al or oxygen and are therefore contaminated. Therefore, the electrical characteristics and crystallinity of the semiconductor layer epitaxially grown on the sapphire substrate are significantly degraded. For this reason, the performance of the sapphire substrate as a practical substrate is hampered, and the reality is that it has not been fully put into practical use.

この様な状況を鑑みて、本出願人は先にサフア
イア基板全面に比較的質量数の小さいY,Ca,
Mg,Scなどを添加した安定化ジルコニア薄膜を
被覆してなる新しい半導体用絶縁基板を特願昭59
−187661、特願昭60−7032等として提案し、半導
体デバイスの特性に影響を及ぼさない半導体用絶
縁基板を実現している。
In view of this situation, the present applicant first coated the entire surface of the sapphire substrate with Y, Ca, and
Patent application for a new semiconductor insulating substrate coated with a stabilized zirconia thin film doped with Mg, Sc, etc.
-187661, Japanese Patent Application No. 60-7032, etc., and realized an insulating substrate for semiconductors that does not affect the characteristics of semiconductor devices.

<発明が解決しようとする問題点> しかし、本出願人が先に提案した半導体用絶縁
基板において、安定化ジルコニア薄膜を形成させ
る場合、成長温度が550℃以上と高く、また酸化
物の添加範囲も6.2モル%〜12.6モル%と比較的
狭い範囲であり、安定化ジルコニア薄膜の形成条
件に制約があつた。
<Problems to be Solved by the Invention> However, when forming a stabilized zirconia thin film in the insulating substrate for semiconductors previously proposed by the present applicant, the growth temperature is as high as 550°C or higher, and the addition range of oxides is too high. The content was also within a relatively narrow range of 6.2 mol% to 12.6 mol%, which placed restrictions on the conditions for forming the stabilized zirconia thin film.

本発明は、上記の点に鑑みて創案されたもので
あり、本出願人が先に提案した半導体用絶縁基板
において用いた安定化剤よりもさらに低温、添加
範囲を広げる安定化剤を用いることにより容易に
形成した安定化ジルコニア薄膜をサフアイア基板
に被覆してなる半導体用絶縁基板を提供すること
を目的としている。
The present invention was devised in view of the above points, and uses a stabilizer that can be added at a lower temperature and has a wider range of addition than the stabilizer used in the semiconductor insulating substrate previously proposed by the applicant. An object of the present invention is to provide an insulating substrate for a semiconductor, which is formed by coating a sapphire substrate with a stabilized zirconia thin film that is easily formed.

<問題点を解決するための手段> 上記の目的を達成するため、本発明の半導体用
絶縁基板は、サフアイア基板全面にイツトリウム
(Y)より質量数の大きい希土類の元素を含む安定化
剤を含有量6.1モル%〜19.4モル%添加した安定
化ジルコニアの単結晶膜を被覆してなるように構
成している。
<Means for Solving the Problems> In order to achieve the above object, the insulating substrate for semiconductors of the present invention includes yttrium on the entire surface of the sapphire substrate.
It is constructed by coating a single crystal film of stabilized zirconia to which a stabilizer containing a rare earth element having a mass number larger than (Y) is added in a content of 6.1 mol % to 19.4 mol %.

また、本発明の実施態様として本発明に係る半
導体用絶縁基板はサフアイア基板全面に、質量数
150.3〜173.0とイツトリウム(Y)より大きい安定化
剤サマリウム(Sm)、ガドリニウム(Gd)、イツ
テルビウム(Yb)を添加した酸化ジルコニウム
によつて形成した安定化ジルコニアの単結晶を被
覆するようにしたものである。
In addition, as an embodiment of the present invention, the semiconductor insulating substrate according to the present invention has a mass number of
A single crystal of stabilized zirconia formed from zirconium oxide added with stabilizers samarium (Sm), gadolinium (Gd), and ytterbium (Yb), which are larger than yttrium (Y) with a value of 150.3 to 173.0, is coated. It is something.

<作 用> 本発明に係る半導体用絶縁膜の構造は、サフア
イア基板全面に、酸化物単結晶の安定化ジルコニ
ア膜に覆われている。安定化ジルコニア膜の形成
に際し、イツトリウム(Y)より質量数の大きい安定
化剤の添加により、成長温度の低減や添加量の拡
大などの点で、本出願人が先に提案したものより
有利でである。また、半導体用絶縁基板として採
用した場合でも、たとえ高温(〜1200℃)に上げ
て、シリコン等の半導体材料をエピタキシヤル成
長させても、内部のサフアイアは安定なジルコニ
アに覆われているため、直接活性な水素に晒され
ることもなく還元反応は生じない。更に、基板表
面に形成された安定化ジルコニア薄膜は活性な水
素に対して安定であるため、シリコン等の半導体
エピタキシヤル成長層にジルコニウム(Zr)や
酸素(O2)等の汚染を与えることなく高純度の
エピタキシヤル膜が得られる。従つて、本発明に
係る構造の絶縁基板をシリコン等の半導体デバイ
スに適用させることにより、素子間分離が容易と
なり、しかもラツチアツプフリーとなるため、超
高速で高密度、高集積のバイポーラトランジスタ
やBi−CMOS,CMOS等のVLSIの作成が可能と
なる。
<Function> In the structure of the semiconductor insulating film according to the present invention, the entire surface of the sapphire substrate is covered with a stabilized zirconia film made of an oxide single crystal. When forming a stabilized zirconia film, the addition of a stabilizer with a larger mass number than yttrium (Y) is more advantageous than the method previously proposed by the applicant in terms of lowering the growth temperature and increasing the amount added. It is. Furthermore, even when used as an insulating substrate for semiconductors, even if semiconductor materials such as silicon are epitaxially grown at high temperatures (~1200℃), the internal sapphire is covered with stable zirconia. There is no direct exposure to active hydrogen and no reduction reaction occurs. Furthermore, since the stabilized zirconia thin film formed on the substrate surface is stable against active hydrogen, it can be used without contaminating the epitaxial growth layer of semiconductors such as silicon with zirconium (Zr) or oxygen (O 2 ). A highly pure epitaxial film can be obtained. Therefore, by applying the insulating substrate having the structure according to the present invention to a semiconductor device made of silicon or the like, it becomes easy to isolate between elements, and it becomes latch-up free. It becomes possible to create VLSI such as Bi-CMOS and CMOS.

<実施例> 以下、図面を参照して、本発明の一実施例につ
いて詳細に説明する。
<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は、本発明に係る半導体用絶縁基板の基
本構造を図式的に示した断面図である。
FIG. 1 is a sectional view schematically showing the basic structure of an insulating substrate for semiconductors according to the present invention.

第1図において、サフアイア基板1の全面に単
結晶の安定化ジルコニア膜2(ZrO21-o
(Yb2O3o又は、(ZrO21-o(Sm2O3o,(ZrO21-
(Gd2O3oが被覆される。ただしnの値は0.061
から0.194の間である。
In FIG. 1, a single crystal stabilized zirconia film 2 (ZrO 2 ) 1-o is formed on the entire surface of a sapphire substrate 1.
(Yb 2 O 3 ) o or (ZrO 2 ) 1-o (Sm 2 O 3 ) o , (ZrO 2 ) 1-
o (Gd 2 O 3 ) o is coated. However, the value of n is 0.061
and 0.194.

スパツタ法を用いると、母体材料である酸化ジ
ルコニウムZrO2は成長温度400℃以上でエピタキ
シヤル成長するが、この酸化ジルコニウムZrO2
の単結晶膜は、結晶系が単斜晶であり、高温にな
ると正方晶になり、更に高温になると立方晶に相
転移を起すことが知られている。そのため温度履
歴によつては7.4%もの体積膨張が生じ、自己破
壊を起してしまう。しかしながら酸化ジルコニウ
ムZrO2の中に安定化剤として、イツトリウム(Y)
より質量数の大きい元素を含んだ酸化イツテルビ
ウム(Yb2O3)、酸化サマリウム(Sm2O3)、酸化
カドリニウム(Gd2O3)のうちの1種類を6.1モ
ル%〜19.4モル%の範囲で添加することにより、
成長温度450℃〜1000℃で立方晶の単結晶膜が得
られる。この安定化ジルコニア膜は温度履歴に対
しても、同一の結晶構造を維持することが判明し
た。本発明の特徴は、イツトリウム(Y)より質量数
の大きな安定化剤を添加したジルコニア膜2を好
ましくはスパツタ法により膜厚が0.01〜10μmの
範囲でサフアイア基板1上に形成させた構造にあ
る。
When using the sputtering method, the base material zirconium oxide ZrO 2 grows epitaxially at a growth temperature of 400°C or higher ;
It is known that the single-crystalline film has a monoclinic crystal system, which changes to a tetragonal crystal at high temperatures, and undergoes a phase transition to a cubic crystal at higher temperatures. Therefore, depending on the temperature history, a volume expansion of as much as 7.4% may occur, leading to self-destruction. However, yttrium (Y) is added as a stabilizer in zirconium oxide ZrO2 .
6.1 mol% to 19.4 mol% of one of ytterbium oxide (Yb 2 O 3 ), samarium oxide (Sm 2 O 3 ), and cadrinium oxide (Gd 2 O 3 ) containing elements with higher mass numbers. By adding within the range,
A cubic single crystal film can be obtained at a growth temperature of 450°C to 1000°C. It was found that this stabilized zirconia film maintains the same crystal structure despite temperature history. The present invention is characterized by a structure in which a zirconia film 2 to which a stabilizer having a mass number larger than yttrium (Y) is added is formed on a sapphire substrate 1, preferably by a sputtering method, to a film thickness in the range of 0.01 to 10 μm. .

特に、単結晶の安定化ジルコニア膜2は、高温
に耐え、しかも熱衝撃に強い。また、シリコンと
の格子のミスマツチは4%以内とサフアイア基板
よりは小さいため、格子の整合性は良い。
In particular, the single-crystal stabilized zirconia film 2 can withstand high temperatures and is resistant to thermal shock. Furthermore, the lattice mismatch with silicon is within 4%, which is smaller than that of the sapphire substrate, so the lattice matching is good.

次に、本発明に係る半導体用絶縁基板を用いた
シリコン半導体基板の製造過程を第2図と共に説
明する。
Next, the manufacturing process of a silicon semiconductor substrate using the semiconductor insulating substrate according to the present invention will be explained with reference to FIG.

第2図において、シリコン等の半導体エピタキ
シヤル膜12が半導体用絶縁基板11上にモノシ
ラン(SiH4)、4塩化硅素(SiCl4)、トリクロル
シラン(SiHCl3)などの半導体原料ガスを使用
し、基板温度950℃〜1200℃に加熱して基板全面
に亘つて、0.3〜20μmの範囲内の厚さに形成す
る。形成されたエピタキシヤル膜12は、前述の
如く、サフアイア基板1からのAlや酸素等の汚
染の心配もなく、良好な電気的特性や結晶性を示
す。なお、本発明はシリコン半導体デバイスだけ
でなく、GaAsやInP,SiCなどの化合物半導体デ
バイスにも適用出来ることは言うまでもない。
In FIG. 2, a semiconductor epitaxial film 12 such as silicon is formed on a semiconductor insulating substrate 11 using a semiconductor raw material gas such as monosilane (SiH 4 ), silicon tetrachloride (SiCl 4 ), or trichlorosilane (SiHCl 3 ). The substrate is heated to a temperature of 950° C. to 1200° C. and formed to a thickness within the range of 0.3 to 20 μm over the entire surface of the substrate. As described above, the formed epitaxial film 12 is free from contamination with Al, oxygen, etc. from the sapphire substrate 1, and exhibits good electrical characteristics and crystallinity. It goes without saying that the present invention is applicable not only to silicon semiconductor devices but also to compound semiconductor devices such as GaAs, InP, and SiC.

<発明の効果> 以上のように本発明によれば、安定化ジルコニ
ア薄膜の成長温度を低減し、安定化剤の添加領域
を広げるなど容易に立方晶のジルコニア膜が得ら
れ、更に、半導体デバイスに使用する際に、半導
体デバイスの性能に悪影響を及ぼさない半導体用
絶縁基板を提供することが出来る。
<Effects of the Invention> As described above, according to the present invention, a cubic zirconia film can be easily obtained by lowering the growth temperature of the stabilized zirconia thin film, expanding the area where the stabilizer is added, and further improving the stability of semiconductor devices. It is possible to provide an insulating substrate for semiconductors that does not adversely affect the performance of semiconductor devices when used for.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体用絶縁基板の基本
構造を示す断面図、第2図は、本発明に係る半導
体用絶縁基板を用いたシリコン半導体基板の断面
を示す図である。 1:サフアイア基板、2:単結晶の安定化ジル
コニア膜、11:半導体用絶縁基板、12:シリ
コン等の半導体エピタキシヤル膜。
FIG. 1 is a cross-sectional view showing the basic structure of an insulating substrate for semiconductors according to the present invention, and FIG. 2 is a cross-sectional view of a silicon semiconductor substrate using the insulating substrate for semiconductors according to the present invention. 1: Sapphire substrate, 2: Single crystal stabilized zirconia film, 11: Insulating substrate for semiconductor, 12: Semiconductor epitaxial film such as silicon.

Claims (1)

【特許請求の範囲】 1 サフアイア基板全面にイツトリウム(Y)より質
量数の大きい元素を含む安定化剤を含有量6.1モ
ル%〜19.4モル%添加した安定化ジルコニアの単
結晶膜を被覆してなることを特徴とする半導体用
絶縁基板。 2 前記安定化剤として酸化ジルコニウムZrO2
中に酸化イツテルビウムYb2O3、酸化サマリウム
Sm2O3、酸化ガドリニウムGd2O3のうち1種類の
安定化剤を添加してなることを特徴とする特許請
求の範囲第1項記載の半導体用絶縁基板。
[Scope of Claims] 1 The entire surface of a sapphire substrate is coated with a stabilized zirconia single crystal film to which a stabilizer containing an element with a mass number higher than yttrium (Y) is added in a content of 6.1 mol% to 19.4 mol%. An insulating substrate for semiconductors characterized by the following. 2 Zirconium oxide ZrO 2 as the stabilizer
Itterbium oxide Yb 2 O 3 and samarium oxide inside
The insulating substrate for a semiconductor according to claim 1, wherein one type of stabilizer selected from Sm 2 O 3 and gadolinium oxide Gd 2 O 3 is added.
JP3142286A 1986-02-14 1986-02-14 Insulating substrate for semiconductor Granted JPS62189747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3142286A JPS62189747A (en) 1986-02-14 1986-02-14 Insulating substrate for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3142286A JPS62189747A (en) 1986-02-14 1986-02-14 Insulating substrate for semiconductor

Publications (2)

Publication Number Publication Date
JPS62189747A JPS62189747A (en) 1987-08-19
JPH0584675B2 true JPH0584675B2 (en) 1993-12-02

Family

ID=12330810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3142286A Granted JPS62189747A (en) 1986-02-14 1986-02-14 Insulating substrate for semiconductor

Country Status (1)

Country Link
JP (1) JPS62189747A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523587A (en) * 1993-06-24 1996-06-04 At&T Corp. Method for low temperature growth of epitaxial silicon and devices produced thereby

Also Published As

Publication number Publication date
JPS62189747A (en) 1987-08-19

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