JPH0587181B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to multilayer plastic chip carriers used for packaging electronic components.

[Conventional technology]

Multi-layer plastic chip carriers are used as chip carriers such as plastic pin grid arrays (PPGAs) and plastic cleedless chip carriers (PLCCs) used to package electronic components such as IC chips. There is. As shown in FIGS. 5a and 5b, this multilayer plastic chip carrier A includes a substrate 1 having a cavity recess 10 in the center and an opening 11 larger than the cavity recess 10 in the center. It is formed by laminating and bonding the provided substrates 1 (one or more) using an adhesive layer 3, and the circuit 2 is formed on the upper and lower surfaces of each substrate 1 by etching copper foil or the like.
is formed. Of the circuits 2 formed on the substrate 1, the circuits sandwiched between the upper and lower substrates 1, 1 are present in the inner layer of the multilayer plastic chip carrier A, and therefore become inner layer circuits 2a, and are formed on the upper and lower surfaces of the multilayer plastic chip carrier A. What is exposed to becomes the outer layer circuit 2b. The inner layer circuits 2a of the lowest substrate 1a provided with the cavity recess 10 of the substrate 1 are formed in large numbers radially around the cavity recess 10, and the end on the cavity recess 10 side is an inner layer circuit 2a. Another substrate 1b as part 12
It is made to protrude into the opening 11 of. In the multilayer plastic chip carrier A formed in this way, an electronic component 13 such as an IC chip is mounted in the cavity recess 10, and the electronic component 13 is mounted between the inner lead portion 12 of the inner layer circuit 2a of the substrate 1a and the electronic component 13. The electronic component 13 and the inner layer circuit 2a are electrically connected by applying wire bonding 14 or the like to the inner layer circuit 2a. This inner layer circuit 2a is connected to terminal pins etc. that serve as connections to the outside.
When mounting the multilayer plastic chip carrier A on a motherboard or the like, the electronic component 13 can be electrically connected to the motherboard via the inner layer circuit 2a.

[Problem to be solved by the invention]

And this multilayer plastic chip carrier A
The problem is that the adhesion between the upper and lower substrates 1 is poor. That is, the upper and lower substrates 1 are formed by heat-pressing molding with the adhesive layer 3 such as prepreg for bonding sandwiched therebetween.
However, due to the presence of the circuit 2 (inner layer circuit 2a) provided on the substrate 1 (substrate 1a), the adhesive layer 3 and the substrate are bonded together as shown in FIG. 6b. A gap 20 is created between the electronic component 1 and the electronic component 1.
There is a risk that the performance or reliability of 3 may be degraded. In particular, if the distance l between adjacent circuits 2 is large, the gap between the circuits 2 cannot be filled with the adhesive layer 3, so that gaps 20 occur more often. Therefore, in order to prevent the occurrence of the gap 20, the thickness of the adhesive layer 3 is set thick.
If the thickness of the adhesive layer 3 is increased in this way, the adhesive layer 3
As shown in FIG. 7, the adhesive resin may protrude and cover the inner lead portion 12 of the circuit 2, making it impossible to perform wire boarding 14 between the circuit 2 and the electronic component 13. The present invention has been made in view of the above points, and there is no need to make the adhesive layer 3 thick.
It is an object of the present invention to provide a multilayer plastic chip carrier which can be formed by stacking substrates 1 one above the other without fear of creating a gap between the substrate 1 and the substrate 1.

[Means to solve the problem]

The present invention is a multilayer plastic chip carrier formed by providing a large number of circuits 2, 2... on a plurality of upper and lower substrates 1, 1... and laminating and bonding each substrate 1 with an adhesive layer 3. In A, the width of the circuit 2 located between the upper and lower substrates 1 is formed to be larger than the width of the gap between adjacent circuits 2 to reduce the gap between the circuits 2, and the substrate 1 is Adhesive layer 3 via insulating layer 4 applied to the surface
This is characterized in that the substrates 1 are laminated and bonded together using a method.

[Effect]

In the present invention, the substrate 1 is arranged so as to cover the circuit 2.
By applying the insulating layer 4 on the surface of the circuit, the gap between the adjacent circuits 2 can be filled. In particular, by forming the width of the circuit 2 to be larger than the width of the gap between the adjacent circuits 2, the gap between the circuits 2 and 2 can be filled. By reducing the gap between the circuits 2 and 2, the gap between the circuits 2 can be reliably filled with the insulating layer 4, and by making the surface of the substrate 1 smooth and laminating and bonding the substrates 1 with the adhesive layer 3, the circuits 2 can be tightly bonded. Each substrate 1 can be laminated with good performance.

【Example】

The present invention will be explained in detail below with reference to embodiments shown in FIGS. 1 to 4. The substrate 1 is formed of a resin laminate covered with metal foil, such as a copper-clad epoxy laminate, and a large number of circuits 2 are formed on each substrate 1 by etching the metal foil. There is. here,
Multilayer plastic chip carrier A of the board 1
A cavity recess 10 is provided in the center of the upper surface of the substrate 1a located in the lower layer of the substrate 1.
The inner layer circuit 2a formed on the upper surface of a is provided in a radial pattern centered on the cavity recess 10, and as shown in FIG. The other end is close to the end of the board 1a as a land 16 provided with a through-hole portion 15 (in FIG. 3, the circuit 2a is shown only in a part of the board 1a). , other parts are omitted from the drawings.) First, an insulating layer 4 is formed on the upper surface of this substrate 1a. The insulating layer 4 can be formed using a solder resist or the like, and the insulating layer 4 is formed by applying a liquid solder resist to the upper surface of the substrate 1a and heating and curing it as necessary. can do. By coating and forming the insulating layer 4 in this way, the inner layer circuit 2a formed on the upper surface of the substrate 1a as shown in FIG.
The gaps between adjacent ones can be filled with the insulating layer 4, and the upper surface of the substrate 1a can be made smooth. Here, the narrower the interval between the circuits 2a, the smaller the gap between the circuits 2a, so the gap can be reliably filled with the insulating layer 4, and the interval l between the circuits 2a is 2 mm or less. It is recommended to set it to . When forming the circuit 2 on the substrate 1 by etching a metal foil such as copper foil, the circuit 2 is usually formed by etching the other parts, leaving a width necessary for the signal line. However, in the present invention, by etching the width of the circuit 2 while leaving it wider than the width required for the signal line, the width of the circuit 2 is increased to the width between the adjacent circuits 2, as shown in FIG. As a result, the distance between adjacent circuits 2 can be set to be as narrow as 2 mm or less. The interval may be set to a narrow width of 2 mm or less for all of the circuits 2 formed on the substrate 1, but it is set in this way at least for the inner layer circuit 2a that will be sandwiched between the substrates 1. . Furthermore, it is desirable to set the width of the circuit 2 to be wider than the interval between the circuits 2 over the entire surface of the board 1 as much as possible, and this is always necessary in the area close to the inner lead part 12, but of course, over the entire surface of the board 1 This is not required; for example, in areas where through-holes are formed, the width of the circuits 2 is often set smaller than the width of the interval between the circuits 2, and approximately 80% of the board 1 is The width dimension of the circuit 2 may be set wider than the interval dimension of the circuit 2 in terms of area. After coating and forming the insulating layer 4 on the upper surface of the substrate 1a as described above, an adhesive layer 3 is placed on the substrate 1a.
The substrates 1b provided with the openings 11 are laminated and bonded together. The adhesive layer 3 can be formed of, for example, prepreg (resin-impregnated dry base material) for bonding, and by sandwiching the prepreg between the upper and lower substrates 1 and heat-pressing molding, it is possible to bond multiple upper and lower substrates. A multilayer plastic chip carrier A as shown in FIG. 2 can be obtained by laminating and bonding 1 with an adhesive layer 3. The surface of the substrate 1 is an insulating layer 4
Since the adhesive layer 3 and the surface of the substrate 1 are smoothed by coating, there is no possibility that a gap will be formed between the adhesive layer 3 and the surface of the substrate 1. Further, since it is possible to prevent a gap from forming between the adhesive layer 3 and the substrate 1 in this way, there is no need to use a thick adhesive layer 3, and the substrate 1b
There is no fear that the inner lead portion 12 of the inner layer circuit 2a protruding into the opening 11 of the inner lead portion 12 will be covered by the protrusion of the adhesive layer 3. In the embodiments shown in FIGS. 1 to 4, the inner layer circuit 2a is not formed on the substrate 1b provided with the opening 11, but in the embodiments shown in FIGS.
Needless to say, the present invention is also applicable to the case where the inner layer circuit 2a is formed on the substrate 1b as shown in FIG.
At this time, the insulating layer 4 is also applied and formed on the substrate 1b side.

【Effect of the invention】

As described above, in the present invention, each board is laminated and bonded by an adhesive layer through an insulating layer applied to the surface of the board so as to cover the circuit.
The gap between adjacent circuits can be filled by applying an insulating layer to the surface of the substrate so as to cover the circuits, and in particular, forming the width of the circuit to be larger than the width of the gap between adjacent circuits. By reducing the spacing between the circuits, the gap between the circuits can be reliably filled with an insulating layer, and the surface of the board can be smoothed with the insulating layer, and then the boards can be laminated and bonded using the adhesive layer. This allows each substrate to be laminated with good adhesion without creating a gap between the adhesive layer and the substrate.

[Brief explanation of drawings]

Figure 1 is an enlarged cross-sectional view of the section A--I in Figure 2;
FIG. 2 is a sectional view of an embodiment of the present invention, FIG. 3 is a plan view of the same board, FIG. 4 is an enlarged view of a part of the circuit on the board, and FIGS. 5a and 5b are multilayer plastic chip carriers. FIG. 6a is an enlarged sectional view of a part of the conventional example, FIG. 6b is a sectional view of the Ro-Ro line part of FIG. 6a, and FIG. 7 is a part of another conventional example. It is an enlarged sectional view. 1 is a substrate, 2 is a circuit, 3 is an adhesive layer, and 4 is an insulating layer.

Claims (1)

[Scope of Claims] 1. In a multilayer plastic chip carrier formed by providing a large number of circuits on each of a plurality of upper and lower boards and laminating and bonding each board with an adhesive layer, a circuit located between the upper and lower boards. The width of the circuit is formed to be larger than the width of the gap between adjacent circuits to reduce the gap between the circuits, and each board is bonded with an adhesive layer through an insulating layer coated on the surface of the board so as to cover the circuit. A multilayer plastic chip carrier characterized by being made by laminating and bonding. 2. The multilayer plastic chip carrier according to claim 1, wherein the distance between adjacent circuits is 2 mm or less.