JPH058987B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal storage device such as a digital oscilloscope, a waveform storage device (waveform digitizer), or a logic analyzer, in which a digital signal corresponding to an input signal is stored in a storage circuit. Concerning a measuring device.

[Prior Art] Digital oscilloscopes and waveform storage devices convert an analog input signal into a digital signal and then store this digital signal in a storage circuit consisting of a storage element such as a random access memory (RAM). There is. Furthermore, in a logic analyzer, input digital signals are stored in a storage circuit. By utilizing the memory circuit in this way, the signal storage measurement device can measure the input signal before the trigger point, and can also perform various measurements by processing the digital signal stored in the memory circuit with a computer.

By the way, as the frequency of the input signal to be measured (analog or digital) increases, the storage circuit must also store the digital signal (converted or input) at high speed. However, there is a limit to the maximum writing speed of the memory elements that make up the memory circuit, and high-speed digital signals cannot be stored. Therefore, in the past, as disclosed in Japanese Patent Publication No. 56-43543, a plurality of storage elements were used for one digital signal to equivalently increase the maximum writing speed. That is, a serial input digital signal is converted into an N-bit (N is an integer of 2 or more) parallel digital signal using a serial-to-parallel conversion circuit such as a shift register, and a serial input signal is converted into a parallel digital signal of N bits (N is an integer of 2 or more). The parallel digital signal from the parallel conversion circuit is latched by a latch circuit, and each bit of the latched N-bit parallel signal is stored in each of the N storage elements. Therefore, the period of each bit (corresponding to each clock) of the serial input digital signal is extended by N times, so
The maximum write speed of the entire memory circuit could be made N times faster than the maximum write speed of each memory element.
By utilizing this technique, the signal storage measurement device was able to measure signals under test at very high frequencies.

[Problems to be solved by the invention] When N is, for example, 4 in the above-mentioned memory circuit,
The first, second, third and fourth bits (clocks) of the serially input digital signal are simultaneously stored at the same addresses of the first, second, third and fourth storage elements, respectively; , sixth, seventh and eighth bits (clocks) are simultaneously stored at the next addresses of the first, second, third and fourth storage elements, respectively. From now on, repeat this operation. by the way,
In the signal storage measurement device, the capture (write) operation of the storage circuit is controlled according to the trigger point. Therefore, it is extremely important for measurements to know the storage location in the storage circuit where the serial input digital signal corresponding to the trigger point is stored. However, in conventional signal storage measurement devices, 4 clocks worth of 4-bit (N = 4) digital signals are stored at the same address in 4 storage elements at the same time, so which storage location corresponds to the trigger generation point. It was difficult to determine whether

[Means for Solving the Problems] The signal storage measuring device of the present invention includes a first serial-to-parallel conversion circuit that converts a serial digital signal into an N-bit (N is an integer of 2 or more) parallel digital signal; A latch circuit that latches the parallel digital signal from the 1-serial-to-parallel conversion circuit, a storage circuit that stores the parallel digital signal from this latch circuit, an address generator that generates an address signal for this storage circuit, and a trigger point. A trigger circuit for detection, a storage control circuit for controlling the storage operation of the storage circuit according to the output signal of the trigger circuit, and a second serial-to-parallel conversion circuit for receiving the output signal of the trigger circuit and converting it into an N-bit parallel digital signal. and a judgment circuit that judges whether the trigger circuit has detected a trigger point every N bits (clocks) of the serial digital signal and generates an output signal when the trigger point is detected, and this judgment circuit generates an output signal. and processing means for determining the storage position of the storage circuit corresponding to the trigger point according to the parallel digital signal from the second serial-to-parallel conversion circuit and the address signal from the address generator when the trigger point is reached.

[Operation] According to the signal storage measurement device of the present invention, a digital signal corresponding to an input signal, that is, a digital signal obtained by converting an analog input signal in a digital oscilloscope and a waveform storage device, and a digital input signal in a logic analyzer. At the same time, the output signal of the trigger circuit is also converted from serial to parallel. Therefore, the respective bits of the parallel output signals of the first and second serial-to-parallel conversion circuits correspond in terms of timing. Also, every N bits (clocks) of the digital signal corresponding to the input signal, N clocks of this digital signal are simultaneously stored in the memory circuit, so whether the trigger point is detected every N bits (clocks) period or not. is making a judgment. Therefore, from the output state of the second serial-to-parallel converter circuit when the trigger point is detected,
It can be determined which bit of the parallel digital output signal of the first serial-to-parallel converter circuit (ie, which storage element of the storage circuit) the bit at the trigger point corresponds to. Therefore, from the output state of the second serial-to-parallel conversion circuit when this trigger point is detected and the address signal of the address generator when the trigger is generated, the storage position of the storage circuit corresponding to the trigger point (i.e., which (which address of the memory element) can be determined.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a first preferred embodiment in which the present invention is applied to a digital oscilloscope or a waveform storage device. A central processing unit (CPU) 12 connected to a bus (consisting of control lines, data lines, and address lines) 10 provides control/processing means for controlling the operation of the entire signal storage measuring device and for performing various processes. It consists of a read-only memory (ROM) 14 that stores programs for the CPU, a random access memory (RAM) 16 that serves as a temporary storage device, a keyboard 18 that serves as an input device, and a display 20 that displays measurement results. . This control/processing means is
Signal TB that controls the clock frequency when capturing input signals, control signal when starting capture
ACQ and R also occur.

On the other hand, the analog input signal to be measured at the input terminal 22 is supplied to an analog-to-digital (A/D) converter 24 and a comparator 26 . A/D converter 24 converts the analog input signal to a 10-bit digital signal each time a clock signal from time base circuit 28 is generated. This time base circuit 28
The clock signal frequency of is determined by the control signal TB. Comparator 26 compares the analog input signal with the variable DC voltage from potentiometer 30 that determines the trigger level, and when the analog input signal exceeds the variable DC voltage, i.e., detects the trigger point, its output level is changes from "low" level to "high" level. Flip-flop 32 is reset by control signal R when input signal acquisition begins and is set by the rising edge of the output signal of comparator 26. Thus, the Q output signal of flip-flop 32 is at a "low" level before the trigger point and becomes a "high" level after the trigger point. These comparator 26 and flip-flop 32 constitute a trigger circuit.

Each time the latch circuit 34 receives the clock signal from the time base circuit 28 via the delay element 36, it receives the 10-bit digital signal from the A/D converter 24 and the 1-bit digital signal from the flip-flop 32. Latch. Note that the delay element 36 compensates for the delay time of the A/D converter 24. A 10-bit digital signal corresponding to the input signal latched to the latch circuit 34 is supplied to a shift register (S/R) 38, and a 1-bit digital signal, which is the output signal of the trigger circuit, is supplied to a shift register 40. supply These shift registers 38 and 40 are serial-input parallel registers that sequentially shift the input digital signal to generate a 4-bit parallel digital signal in response to a clock signal from the time base circuit 28 via delay elements 36 and 42. Works as an output type serial/parallel conversion circuit. In particular, the shift register 38 receives a 10-bit parallel digital signal and performs serial-to-parallel conversion on each bit, so it is composed of 10 shift register elements. Note that the delay element 42 compensates for the propagation delay time of the latch circuit 34.

The output signal of the shift register 38, that is, a total of 40 bits of output signal in which each bit of the 10-bit input signal is converted into 4 bits in parallel, is sent to the latch circuit 4.
4, and the 4-bit output signal of shift register 40 is supplied to latch circuit 46. one quarter
Frequency divider 48 divides the frequency of the clock signal from delay element 42 by a factor of four and controls the latching operation of latch circuits 44 and 46. Therefore, the combination 38- of these shift registers and latch circuits
44 and 40-46, the period of each bit (clock) of the output signal of the latch circuit 38, that is, the digital signal according to the input signal and the digital signal from the trigger circuits 26-32, is expanded by four times. Become. The storage circuit (memory) 50 is composed of four memory elements (RAM) that can store a 10-bit word at one address, and these memory elements are addressed by the same address signal, and the output digital signal of the latch circuit 44 is (four 10-bit digital words) are stored sequentially. The combination of shift register 38, latch circuit 44 and memory 50 is the same as that disclosed in Japanese Patent Publication No. 56-43543 mentioned above.

However, in the present invention, the following configuration is added so that the storage location in the memory 50 where the digital signal at the time of generation of the trigger signal is stored can be easily determined. That is, the OR gate 52 receives the input signal and the oldest output signal of the shift register 40 (i.e., the current trigger output signal and the trigger output signal three clocks ago), and outputs the output signal from the D.
It is supplied to the D terminal of flip-flop 54. Each time flip-flop 54 receives a clock signal from quarter divider 48 at its clock terminal, it outputs the output signal of OR gate 52 as a Q output. Therefore, the OR gate 52 and the flip-flop 54 determine whether the trigger circuit 26-32 has detected the trigger point by using the N clocks of the input signal.
That is, it is a judgment circuit that makes a judgment every N bits (4 bits in this embodiment) and generates an output signal when a trigger point is detected. Note that the output signal of the trigger circuit changes from "low" level to "high" level at the trigger point.
Note that the level changes and remains at a "high" level after the trigger point.

When the determining means detects a trigger instant, the Q output signal of flip-flop 54 goes to a "high" level, and this "high" level is applied to shift register 40.
is supplied to the hold terminal H of the shift register 40 to hold the state of the shift register 40. Therefore, since the output signal of shift register 40 does not change after the trigger point, latch circuit 46 continues to latch its latched state, ie, the output signal of shift register 40 that includes the trigger point. flip flop 54
continues to be clocked, but or
Since the output level of gate 52 is "high", the Q output signal of flip-flop 54 remains at a "high" level.

On the other hand, since the flip-flop 56 is set by the control signal ACQ at the beginning of receiving the input signal, its Q output is at a "high" level, and the AND gate 58 receives the signal from the quarter frequency divider 48. passes the clock signal. The clock signal from the AND gate 58 is connected to the write enable terminal WE of the memory 50 and the delay counter 6.
0 to address counter 62 and the clock terminal of flip-flop 64. Then,
When the write operation starts, the address counter 62 counts the clock signal whose frequency has been divided into four, and uses the count output as an address signal for the memory 5.
0 address terminal AD. By the way, if a trigger point is detected and the write operation is stopped before a digital signal corresponding to a new input signal is written to all addresses in the memory 50, the newly stored digital signal will be mixed with the previously stored digital signal. digital signals are mixed in the memory 50,
It becomes difficult to measure new input signals. Therefore, in this embodiment, when the address counter 62 writes a new input signal to all addresses of the memory 50, that is, when the first overflow signal is generated (the address counter 62 starts from the lowest address of the memory 50 output up to the maximum address),
Flip-flop 66 is set and its Q output goes high. This "high" level enables flip-flop 32 and
It is designed to be able to respond to the output signal of the comparator 26. In other words, it is not possible to respond to a trigger until input signals are written to all addresses in the memory 50.

The delay counter 60 is connected to the flip-flop 54.
begins counting the clock signal from AND gate 58 when its Q output goes high. The delay counter 60 has a function of stopping the write operation of the memory 50 after counting a desired number of clock signals after the trigger point, so that input signals after the trigger point can also be measured. This desired count value is determined in advance by the control/processing means at the delay counter 6.
Set to 0. That is, once the delay counter 60 has counted the desired number of clock signals, the high
The level is applied to the D terminal of flip-flop 64. Therefore, its Q output also goes high, resetting flip-flop 56 so that AND gate 58 no longer passes the clock signal, address counter 62 and delay counter 60 stop counting, and memory No write enable signal is supplied to 50, and the write operation is stopped.

On the other hand, the multiplexer (MUX) 68 outputs a "low" level when the output of the delay counter 60 is at a "low" level.
Level L is selected, and when the output of delay counter 60 is at the "high" level, the output signal of latch circuit 46 is selected and the selected output signal is supplied to chip select terminal CE of memory 50. The operation of this multiplexer 68 will be described in detail later. These delay counter 60 and multiplexer 68 serve as a storage control circuit. When the input signal has been input to the memory 50, the memory 50 can be loaded as needed.
The stored contents are displayed on the display 20. Note that this display device 20 includes an analog-to-digital converter that converts a digital signal into an analog signal, a display memory,
It is equipped with a display control circuit, etc.

The signal storage measuring device of FIG. 1 configured as described above operates as follows. First, the operator uses the keyboard 18 to set the acquisition clock frequency and the number of delay clocks, and uses the potentiometer 30 to set the trigger level. When a capture start command is then entered from keyboard 18, the control/processing means resets flip-flops 64 and 66 and counters 60 and 62, and sets flip-flop 56. Therefore, flip-flop 32 is disabled and flip-flop 56 is not reset. The control/processing means also generates an ACQ signal to set flip-flop 56 so that AND gate 58 passes the divided-by-four clock signal. Multiplexer 68 is "low"
Since the level is selected, all four memory elements of memory 50 are in operation.

As mentioned above, the shift register 38 and latch circuit 44 limit the period of each bit (clock) to 4.
The doubled digital signal is then
The address signal from the counter 62 is stored in each element of the memory 50. When digital signals are stored in all addresses of each memory element, address counter 62 generates an overflow signal;
Set flip-flop 66. Then,
Flip-flop 32 becomes operational. Thereafter, when the trigger circuit 26-32 detects the trigger point, the output of the flip-flop 32 changes to a "high" level. Then, the trigger output of the latch circuit 34 also changes to a "high" level, so the output of the OR gate 52 also becomes a "high" level. However, since flip-flop 54 is only clocked every four clocks by frequency divider 48, it is clocked by the next output from frequency divider 48, placing shift register 40 in a hold state. In other words, if the trigger point is the 4n+1 (n is any integer) clock, the contents held in the shift register 40 will be 1000 (LSB is the oldest bit), and 4n+2
If the 4n+3rd clock is the trigger point, the content held in the shift register 40 is 1100, if the 4n+3rd clock is the trigger point, the content held in the shift register 40 is 1110, and if the 4n+4th clock is the trigger point, the shift register 40 is 1100. The contents held in register 40 are
1111 or 0000. This digital data held in the shift register 40 is transferred to the latch circuit 46.
is latched to. Note that when the input from the output side of the shift register 40 of the OR gate 52 is at a "high" level, the input from the latch circuit 34 is always at a "high" level, but the contents held in the shift register 40 are As mentioned above, since there are cases of 0000 and 1111, the OR gate 52 is required.

On the other hand, when the Q output of flip-flop 54 goes high, delay counter 60 begins counting. When the counter 60 counts the set number of clocks, the AND gate 58 closes as described above and the counters 60 and 62 stop counting. Also at this time, the multiplexer 68 switches and the output signal of the latch circuit 46 is transferred to the memory 50.
Since it is supplied to the chip select terminal CE of
At the final address of the write operation, the memory element corresponding to the 4m clock (m is the number of delay clocks divided by 1/4) from the trigger point does not perform the write operation. As a result, even though data is written to the memory every 4 clocks, by selectively performing a write operation on memory elements at the same address, the write operation can be accurately stopped at the 4mth clock after the trigger point is detected.

After the input signal capture (write) operation is completed, the contents stored in the memory are displayed on the display 20 or calculated by the CPU 12 as necessary. Also,
The CPU 12 performs the following operations according to the program in the ROM 14. That is, first, the latch circuit 46
, the final address of the address counter 62 is read, and the set value of the delay counter 60 is subtracted from the value of the address counter 62. From this result, the memory address where the trigger point exists can be determined. Also, from the contents of the latch circuit 46 it is known which memory element corresponds to the trigger point. If these are comprehensively judged, the storage location of the memory 50 where the input signal of the trigger point is stored can be determined.

FIG. 2 is a partial block diagram of the signal storage measurement device of the present invention applied to a logic analyzer. In this embodiment, comparators 100 to 11
8 compares the digital signals from input terminals 80-98, respectively, with the threshold voltage from the potentiometer to determine the logic level. Latch circuit 122 is similar to time base circuit 28 of FIG.
The comparators 100 to 118 are controlled by the clock signal from
It latches the output signal and works as a sampling circuit. Word recognizer 124 is a trigger circuit that detects a desired trigger word from the output signal of latch circuit 122, that is, detects a trigger point. Latch circuit 34 receives the output signal of latch circuit 122 via delay element 126, directly receives the output signal of word recognizer 124, and responds to the clock signal from time base circuit 28 via delay element 36. These input signals are latched. Note that the delay element 126 compensates for the propagation delay time of the word recognizer 124. The output signal of latch circuit 34 is applied to shift registers 38 and 40 and OR gate 5 of FIG.
Join 2. Other configurations and operations are the same as in FIG. 1.

FIG. 3 shows a modification of FIG. 2. In this embodiment, each bit of the serial digital signal, ie, the clock, is expanded by 16 times, and the maximum and minimum values for each predetermined period can also be detected. Note that the clock signal from the time base circuit 28 is converted by the push-pull amplifier 130 into signals having a phase difference of 180 degrees. To simply stretch the signal by a factor of 16, multiplexer 140 selects the clock signal from push-pull amplifier 130 and applies it to the clock terminals of latch circuits 132 and 136. On the other hand, the multiplexer 160 is connected to the push-pull amplifier 1.
30 and delay element 148. Latch circuits 132 and 136 alternately latch the output signal of latch circuit 34, and latch circuits 142 and 144 latch the output signal of latch circuit 34, respectively.
36 output signals to these latch circuits 132 and 1
Since it latches at twice the period of 36, the period of each bit (clock) of each digital signal is doubled. The output signals of latch circuits 142 and 144 are each further expanded by a factor of four as in the case of FIG. The circuit configuration for this purpose is the same as that shown in FIG.
Two sets of shift registers are provided for each of the two shift registers. Also, the number of bits in latch circuits 44 and 46 has been increased to 8 bits.

The envelope mode in digital oscilloscopes and waveform storage devices determines maximum and minimum values at predetermined intervals and stores these values. Therefore, in this embodiment, time base circuit 28 provides a high frequency clock signal to latch circuit 34 and push-pull amplifier 130, and a low frequency clock signal to multiplexer 160 via delay element 150. Multiplexer 160 connects delay element 150 and multiplexer 140
provides the output signals of digital comparators 134 and 138 to latch circuits 132 and 136, respectively. The digital comparator 134 generates an output signal when the output signal of the latch circuit 34 is larger than the output signal of the latch circuit 132, and transfers the larger digital signal from the latch circuit 34 to the new latch circuit 132.
to latch. Similarly, digital comparator 138
generates an output signal when the output signal of the latch circuit 34 is smaller than the output signal of the latch circuit 136, and causes the latch circuit 136 to newly latch the smaller digital signal from the latch circuit 34. The digital signals latched in these latches 132 and 136 are latched in latches 142 and 144 each time a low frequency clock signal occurs. Therefore, the maximum and minimum values for each cycle of the lower frequency clock signal can be detected. The output signals of latch circuits 142 and 144 are each expanded four times as in the case of FIG.
Stored as 0.

Although only preferred embodiments of the present invention have been described above, various modifications can be made without departing from the gist of the present invention. For example, the trigger circuit may detect the trigger point from an external trigger signal rather than an input signal. Further, when the present invention is applied to a logic analyzer, the trigger circuit may have a sequential trigger function. Furthermore, the memory circuit can be configured appropriately depending on the data width of the memory element.

[Effects of the Invention] As described above, according to the present invention, even if the bit (clock) period of an input digital signal is extended using a serial-to-parallel conversion circuit and a latch circuit, and the signal is simultaneously stored in a plurality of storage locations, the trigger point can be maintained. You can easily know the storage location where the signal is stored when it is detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first preferred embodiment of the invention, FIG. 2 is a partial block diagram of a second preferred embodiment of the invention, and FIG. 3 is a third preferred embodiment of the invention. FIG. In the figure, 12 to 16 are processing means, 26-3
2 and 124 are trigger circuits, 38 is a first serial-to-parallel conversion circuit, 40 is a second serial-to-parallel conversion circuit, 44 is a latch circuit, 50 is a storage circuit, 62 is an address generator, 52-54 is a judgment circuit, 60- 68 is a storage control circuit.

Claims (1)

[Claims] 1. A first serial/parallel converter circuit that converts a serial digital signal into an N-bit (N is an integer of 2 or more) parallel digital signal, a latch circuit that latches the parallel digital signal from the first serial/parallel converter circuit, and a memory circuit that stores parallel digital signals from the latch circuit; an address generator that generates an address signal for the memory circuit; a trigger circuit that detects a trigger point; a second serial/parallel conversion circuit that receives the output signal of the trigger circuit and converts it into an N-bit parallel digital signal; a judgment circuit that judges every N bits of the digital signal and generates an output signal when the trigger point is detected; and a parallel digital signal from the second serial-to-parallel conversion circuit when the judgment circuit generates the output signal. and processing means for determining a storage position of the storage circuit corresponding to the trigger point in response to an address signal from the address generator.