JPH06100666B2 - Electronic clock - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic timepiece that has a power generation mechanism inside and that operates using electric energy generated by the power generation mechanism.

[Prior Art] As disclosed in Japanese Patent Application No. Sho 59-246778 and the like, an electronic timepiece that has a power generation mechanism inside and uses the generated energy is to effectively use the generated energy without waste. Further, it has a booster and a voltage detector, and optimally controls the boosting ratio based on the voltage detection result. Japanese Patent Application Sho 60-7
No. 6007 has a charge control circuit 32 as shown in FIG. 3, and even if sufficient electric energy is not stored in the first charge storage member 32 (hereinafter referred to as the first capacitor), the charge control circuit 32 An electronic timepiece is disclosed in which the electric charge necessary for the operation of the time counting circuit 36 is stored in the second charge storage member 35 (hereinafter referred to as the second capacitor) by 32, and the operation at the time of starting is facilitated. In this electronic timepiece, when the electric energy is not sufficiently stored in the first capacitor at the time of startup and the generated voltage Vsc is small, the P-channel transistor (hereinafter Pch · Tr) in the charge control circuit is turned off (hereinafter this state). Is kept active), and the voltage obtained by the product of the current generated by the power generation mechanism 31 and the resistance R is stored in the second capacitor and used as the power supply Vss of the clock circuit 36. At this time,
The voltage boosting means 38 is controlled by the voltage detecting means so that the Vss side and the Vss side serve as a cathode diode. Then, when charging progresses and Vsc becomes a voltage higher than the first regulation, Pch-Tr turns on (hereinafter this state is inactive), and the influence of the resistor R disappears and Vsc is first tripled by the boosting means to become Vss. , Next, when Vss becomes the second specified voltage or more, 2
When the voltage is doubled and Vss successively exceeds the second specified voltage, the voltage is boosted to 1.5 times and 1 time to Vss, and the clock circuit 36 continues to operate.

[Problems to be Solved by the Invention] The charge control circuit control and the triple boosting state are performed based on the Vsc voltage detection result by the voltage detecting means, and the other boosting means control is performed based on the Vss voltage detection result. However, when the charging control circuit is in the active state and the electromotive force of the power generation mechanism is large, Vss may exceed the second specified voltage, and charging proceeds and the charging control circuit becomes inactive. There is a possibility that malfunction will occur when it becomes. Here, a concrete example will be given for easy understanding. FIG. 4 shows Vsc and Vss when charging progresses from the start of the electronic timepiece and the state returns to triple boosting or double boosting. During the period from t0 to t1, the charge control circuit is in the active state and the electric energy is gradually stored in the first capacitor. Then, at t1, Vsc is the first specified voltage 0.4V.
After that, the charge control circuit is controlled by the voltage means so that it becomes inactive and triple boosted. Therefore, Vss is about 0.4V × 3 times = 1.2V, but this does not happen suddenly, and since Vss at startup is actually high, Vss
The voltage of sc × 3 times (broken line in the figure) becomes at time t3.
Of course, the time from t1 to t3 becomes shorter as the capacity of the booster increases. Further, t2 indicates a time point when Vss crosses the second specified voltage 1.8V which serves as a reference for switching the boosting state. Therefore, when the Vss voltage is detected between t1 and t2 after the transition from the starting state to the triple boosting state at t1 by the Vsc voltage detection, sufficient electric energy is not stored in the first capacitor and the Vsc voltage is Although it is still low, Vss exceeds the second specified voltage of 1.8V, and the boosted state will shift from 3 times to 2 times. In the example of FIG. 6, Vsc is
Since it is 0.45V or less, if it enters the double boosting state, V
ss becomes 0.9V or less. This voltage is not enough to operate the clock circuit, which causes a problem that the electronic timepiece stops operating.

[Means for Solving the Problems] In the electronic timepiece of the present invention, the voltage detecting means sets the voltage (Vsc) detection sampling of the first charge storage member and the voltage (Vss) detection sampling of the second charge storage member in time. In addition, it is characterized in that the Vss detection sampling is configured to be immediately before the Vsc detection sampling so as to be inconsistent with each other.

[Operation] According to the present invention, the timing of voltage detection sampling is delayed for a certain period of time or more so as to eliminate erroneous voltage detection.

[Embodiment] FIG. 1 is a specific example of the voltage detecting means according to the present invention and its timing chart. The voltage sensing seed means consists of three parts. The sampling timing signal Sig and the clock signal CL generated by one reference signal generator are input to the D-type flip-flop (hereinafter referred to as F / F) in the sampling signal formation 2 and the output of the F / F is NAND. Gate, NOR
Vss sampling signal Sp (Vss) and Vsc detection sampling signal Sp (Vs
c) and formed. Formed sampling signal Sp (V
ss) and Sp (Vsc) are input to the voltage detection unit 3 and the voltage detection unit detects the voltage of Vss and Vsc in a sampling manner according to the signal, and based on the result, the charge control circuit shown in FIG. Take control of the means. In this example, as shown in the timing chart, Sp (Vsc) and Sp (Vss) are always separated by the time t, and this separation time t is defined by the time "L0" of the signal Sig. Therefore, this t is the fourth
The reference signal generator forms the timing of the signal Sig so as to be longer than the time between t1 and t2 in the figure.

FIG. 2 shows another specific example of the voltage detecting means according to the present invention. The basic configuration is the same as that of the specific example shown in FIG. 1, but the components for forming the two sampling signals are different.

In this example, Sp (Vs
s) is located immediately before Sp (Vsc), and the sampling period is the period of the signal Sig. Therefore, in this example as in FIG. 1, the timings of the reference signal generator and the signal Sig are formed so that t is longer than the time between t1 and t2 in FIG.

[Effects of the Invention] If the electronic timepiece having the configuration shown in FIG. 3 is provided with the voltage detecting means as shown in the embodiment, Vsc due to Sp (Vsc) at time t1 in FIG.
The electronic clock is boosted three times by the detection, and Vss gradually increases to Vsc.
Even if the boosting ratio switching voltage is exceeded in the process of approaching the 3 times boosted voltage of Vss, Vss detection by Sp (Vss) takes time.
Since it is performed after t2, there is no problem that the clock circuit operation is stopped due to erroneous detection of Vss. In addition, Vsc
By making the detection and the Vss detection coincident with each other in time, even one detection circuit of the voltage detection unit can be used for detection of both in a time-division manner, so that the circuit load is light and the efficiency is high. The second
In the embodiment, since the time difference t between Vsc detection and Vss detection is set to the maximum possible, the time difference t is assumed to be t1.
Even if it becomes shorter than the time between t2, the electronic watch automatically secures maximum safety, which is a very effective means.

[Brief description of drawings]

1 (a) and 1 (b) are views showing a concrete example of the voltage detecting means according to the present invention. 2 (a) and 2 (b) are diagrams showing another specific example of the voltage detecting means according to the present invention. FIG. 3 is a diagram showing the configuration of a dial clock having a power generation mechanism. Figure 4 is a state transition diagram of Vsc and Vss. 1 ... Reference signal generation unit 2 ... Sampling signal formation unit 3 ... Voltage detection unit 31 ... Power generation mechanism 32 ... Charge control circuit 38 ... Boosting means 33 ... First charge storage member 34 ... Voltage detection Means 35 …… Second charge storage member 36 …… Timer circuit 37 …… Diode 38 …… Boosting means

Claims (2)

[Claims] 1. A) at least an internal power generation mechanism; b) a first charge storage member for storing electrical energy generated by the power generation mechanism; and c) raising and lowering a voltage generated in the first charge storage member. Pressure means and d) a second charge storage member for storing the electric energy generated by the step-up / down means, and e) the voltage generated in the first and second charge members by the sampling operation, and the step-up / down according to the result. In an electronic timepiece having a voltage detecting means for controlling a pressure means, f) the voltage detecting means makes the voltage detection sampling of the first charge storage member and the voltage detection sampling of the second charge storage member temporally disagree. An electronic timepiece characterized by being configured. 2. The method according to claim 1, wherein the voltage detection sampling of the second charge storage member is arranged immediately before the voltage detection sampling of the first charge storage member. Electronic clock.