JPH06100898B2 - Image memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory capable of storing and reproducing a video signal, and more particularly to delaying a sampled and quantized video signal for a predetermined time to perform digital signal processing. The present invention relates to an image memory suitable for execution.

[Prior Art] An image memory for delaying or storing a sampled and quantized image signal for a predetermined time is used as a basic component of a high-quality television system, a high-performance video tape recorder, a digital television system, or the like. It is required to be easy to use and versatile. Conventionally, a plurality of general-purpose dynamic random access memories having a low cost per bit have been used in parallel as the image memory of such a system. However, the storage capacity per chip is 256K
As the capacity increases to 1 Mbit and 1 Mbit, the memory capacity required for image signal processing can be realized with a single chip, and the conventional method of connecting multiple units in parallel reduces the memory capacity utilization efficiency. I will end up. Therefore, recently, Nagami Hara, "320-row x 700-column image-only serial input / output dynamic memory for image memory for TV and VTR field memory", Nikkei Electronics, February 11, 1985, PP21
As described in 9-239, a dedicated dynamic memory that can serially input / output data corresponding to one horizontal scanning line at high speed has been devised. However, even in the above memory, the sampling frequency is four times the color subcarrier frequency (hereinafter, fs).
It is not sufficient for a system referred to as c) or a general video signal processing system that delays or stores a predetermined arbitrary block data for a predetermined time.

[Problems to be solved by the invention]

In the above-mentioned conventional example, a function of randomly accessing at an externally specified address is not added. For example, a picture-and-picture (Pictur & Pictur) function for displaying two different images on the same screen, and a part of the screen If the image memory is used to realize the function of displaying the information, the external circuit configuration becomes extremely complicated.

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to enable high-speed input / output, and to perform multi-functional processing such as multiplexing two different images of a screen divided into two parts, and normal video signal processing. To provide a suitable image memory.

[Means for solving problems]

The above-mentioned object is at least (K ×
m) column n rows (K, m, n is a natural number), and a dynamic memory cell array, and a serial-parallel conversion circuit (hereinafter referred to as an SP conversion circuit) that inputs data in series and outputs m-bit parallel data. , And a parallel-serial conversion circuit (hereinafter referred to as a PS conversion circuit) for inputting m-bit parallel data and outputting in series, and writing for writing the SP-converted parallel data in the memory cell array. An address (hereinafter, referred to as W address), a read address (hereinafter, referred to as R address) for reading parallel data from the memory cell array, and a refresh address (hereinafter, REF address) for refreshing the memory cell array. Is generated in a time division manner, and each address output from the address generation circuit in a time division manner. Address decoding circuit for supplying the address to the memory cell array and a timing control circuit for controlling the timing of each address output from the address generating circuit in a time division manner, and at least reading and writing the address generating circuit. ,
And first to third registers for refresh address (hereinafter, referred to as R register, W register, REF register), and a fifth register for taking in an increase / decrease amount of arbitrary address data or address value. , 1 out of at least 2 of these registers
And a fourth register circuit for taking in the selected register output, and an increment circuit or a decrement circuit for increasing or decreasing the fourth register output value, and first to third Select any one of the output of each register of, and capture in the fourth register,
The process of fetching the data after passing through the increment circuit or the decrement circuit into the register selected again is processed as one cycle of the address generation circuit, and another register output is selected within this one cycle period and the fourth register This is achieved by prohibiting inclusion in the register.

[Action]

By providing a circuit for SP conversion and PS conversion of high-speed serial data at the input / output stage of the dynamic type memory cell array, the writing / reading of the input / output data to / from the memory cell array is converted into, for example, m bits in parallel.
It can be performed at a low speed of 1 / m. Therefore, a read cycle for generating a read address (hereinafter referred to as an R cycle), a write cycle for generating a write address (hereinafter referred to as a W cycle), and a refresh cycle for generating a refresh address (hereinafter referred to as a REF cycle). .) Are provided in time division by the timing control circuit, and the R address, W address, and REF address are supplied in time division from the address generation circuit according to each cycle, and the sum of each cycle is, for example, m bits or less. By selecting, after inputting m serial input data (hereinafter, referred to as D _IN ) m times, W
It becomes possible to allocate a cycle and write it in the memory cell array as m-bit parallel data. Similarly,
It becomes possible to allocate m cycles of serial output data (hereinafter referred to as D _OUT ) and then output m new data, and read m-bit parallel data from the memory cell array. . As described above, continuous writing / reading of high-speed serial data to the memory can be simultaneously performed.

In addition, in the address generation circuit, R register, W register, R register
Fifth with EF register and taking in arbitrary address
Registers are provided, the outputs of these registers are selected in accordance with each of the above cycles, are fetched in the fourth register, and the address value fetched in the fourth register is supplied to the memory cell array through the address decoding circuit. By this, an arbitrary address can be designated according to each cycle, and if not designated, an address value obtained by increasing or decreasing the address value of the previous cycle can be automatically supplied. Therefore, it is necessary to specify arbitrary addresses, for example, 2
It is possible to easily realize multiple functions such as screen functions and multiple small screens.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. First
In one embodiment of the figure, an address arbitrarily specified from the outside is taken in as serial continuous address data (hereinafter, referred to as SAD) to an address generation circuit surrounded by a broken line 33, so that, for example, serial D _IN When m is converted into m-bit parallel data, a random access function in block units with m bits as one block is enabled.

In FIG. 1, 1 is an input terminal for D _IN , 2 is an output terminal for serial output data (hereinafter referred to as D _out ), and 3 is an SP
Conversion circuit, 4 is an input buffer register, 5 is (K × m)
A memory cell array of n rows, 6 is an output buffer register, 7 is a PS conversion circuit, 32 is an address decoding circuit, and the serial D _IN from the terminal 1 is converted into m-bit parallel data by the SP conversion circuit 3, Each bit is transferred to the input buffer register 4. The data transferred to this input buffer register is the W from the address generation circuit 33.
The address is written in the address portion of the memory cell array 5 designated through the address decoding circuit 32 in units of m bits. Similarly, m-bit parallel data of the address portion of the memory cell array 5 designated by the R address from the address generation circuit 33 through the address decoding circuit 32 is read to the output buffer register 6, and the m-bit parallel data is output from the output buffer register 6 to the PS buffer. It is transferred to the conversion circuit 7, converted into a serial D _OUT , and output to the terminal 2. The above memory operation is executed by each address supplied from the address generating circuit 33 in a time-division manner and by the address control circuit 34 surrounded by a broken line which mainly controls the address generating circuit 33.

The operations of the address generation circuit 33 and the address control circuit 34 will be described below.

First, the address generation circuit 33 will be briefly described. In FIG. 1, 8 is an input terminal of SAD, 9 is an input terminal of an SAD strobe signal (hereinafter referred to as SAS) for taking in SAD, and 10 is an arbitrary SAD and SAS from outside. An input terminal of a transfer address strobe signal (hereinafter referred to as TAS) that determines the timing of converting a serial address into a parallel address and transferring the parallel address to the R register 26 or W register 27 of the next stage, 14 is a SAD input register,
24 and 25 are select circuits, 28 is a REF register, 29 is a select circuit, 30 is a memory address register, and 31 is an increment circuit. The address generating circuit 33 of the embodiment of FIG.
Is composed of the above circuits. This address generation circuit 33
Is controlled by each signal from the address control circuit 34,
For example, each cycle for assigning the R address, the W address, and the REF address in time division is set. For each cycle, for example, in the R cycle, each register
From 26 to 29, the output of the R register 26 is the third select circuit 29.
Is selected by, and is guided to the memory address register 30. The output of this register is supplied to the address decoding circuit 32 as an R address, the address value is increased through the increment circuit 31, and then the R value is again passed through the select circuit 24. Taken into register 26. The same processing is performed on the output of the W register 27 in the W cycle and the output of the REF register 28 in the REF cycle.

Next, the address control circuit 34 will be briefly described. In each of the components surrounded by broken lines, 15 and 16 are gate circuits, 17 is a read clock counter (hereinafter referred to as R counter), 18 is a write clock counter (hereinafter referred to as W counter), and 19 is a refresh clock. A counter (hereinafter referred to as REF counter) 20 is a read request signal (hereinafter referred to as RReg) generation circuit, 21 is a write request signal (hereinafter referred to as (WReq)) generation circuit, and 22 is a refresh request signal (hereinafter referred to as WReq). REFReq) generator circuit 23 is a timing generator circuit 23. In this address control circuit 34, the gate circuits 15 and 16 use a clock signal from the terminal 13 (hereinafter referred to as CLK) as a read clock from the terminal 11. The CLK gated by the gate signal (hereinafter, referred to as CGR) and the write clock gate signal (hereinafter, referred to as CGW) from the terminal 12 is used as the read clock (hereinafter, referred to as CCLK). RCLK
Is written. ) And a write clock (hereinafter referred to as WCLK). These RCLK and WCLK are respectively supplied as clock signals for the PS conversion circuit 7 at the output stage and the SP conversion circuit 3 at the input stage, and RCLK and WCLK are respectively supplied.
It is led to the R counter 17 and the W counter 18 which count the PS conversion bit number and the SP conversion bit number. Therefore, the R counter 17 is equivalent to counting the number of D _OUT in which the data transferred in parallel from the output buffer register 6 to the PS converter 7 is serially converted by RCLK, and is equivalent to the number of bits of PS conversion. A signal for starting data transfer from the output buffer register 6 to the PS converter 7 is output every time counting is performed. Further, the W counter 18 is equivalent to counting the number of D _IN serially guided by WCLK to the SP converter 3, and is input from the SP converter 3 every time the number of bits of SP conversion is counted. A signal for starting data transfer to the buffer register 4 is output. The RReg generating circuit 20 and the WReg generating circuit 21 are respectively the R counter 17 in the preceding stage.
Also, the count output of the W counter 18 is received, the RReg signal and the WReg signal are generated respectively, and each control signal is supplied to the address generation circuit 33 according to each Reg signal. REF counter 19
Counts the CLK that is not gated, receives the count output, generates the REFReg signal by the REFReg generating circuit 22, and supplies the refresh address control signal to the address generating circuit 33. The timing generation circuit 23 is a signal generation circuit that determines the generation timing of each control signal that determines the operation cycle of the address generation circuit 33, and divides CLK by 1 / K, for example.
A signal obtained by phase-shifting the 1 / K divided signal for each CLK is used as a timing signal.

Hereinafter, in order to explain the operation of the present invention in FIG. 1 in more detail, the operation timing chart example in FIG. 2 will be described.

In FIG. 2, 2a is a CLK supplied to the terminal 13, 2b is a set signal (hereinafter referred to as SET) guided by SAD, SAS, TAS, etc. of the terminals 8 to 10, and RREG is generated by this SET2b. In the circuit 20, the RReg signal 2c is forcibly generated in synchronization with CLK2a. Also, with this SET2b, R counter 17 and W
Counter 18 is forced to be initially set to a value. In the example of FIG. 2, both counters 17 and 18 and the REF counter are
The 19 count cycles are all 18 clocks, and each bit of SP conversion and PS conversion is also selected as 18.

Each Reg is synchronized with the count cycle of the above counters 17 and 18.
The Reg signals 2c to 2e are generated in the generation circuits 20 to 22. 2
f is 1 of the signal obtained by dividing CLK by 1 / K in the timing generation circuit 23
When K = 6, basically, signals φ _{0 to} φ ₅ having six different phases are obtained, and 2f is φ ₀ of them. 2g shows each cycle, and each Reg signal 2c ~ 2
After e is generated, for example, the first one cycle of φ ₀ 2f is assigned as each cycle. However, for example, when the R cycle and the W cycle occur at the same time, the R cycle is prioritized, the priority is set so that the W cycle occurs after the R cycle, each cycle is assigned in a time-sharing manner, and the cycles do not occur simultaneously To 2h is select circuit 29
Is a read register select signal (hereinafter referred to as RSEL), which is generated in the φ ₁ phase of the R cycle and selects the output of the R register 26 from among the registers 26 to 28 and guides it to the memory address register 30. . Although not shown, in the same manner, in the W cycle, the write register select signal (hereinafter,
It is written as WSEL. ), A refresh register select signal (hereinafter referred to as REFSEL) is generated in the REF cycle,
The outputs of the registers 26 to 28 corresponding to each SEL are selected and guided to the memory address register 30. 2i is each register 26
26 is a latch pulse for fetching the output data of 26 to the memory address register 30, 2j is the memory address data fetched to the memory address register 30 by this latch pulse 2i, and this signal 2j is the address decoder 32 and the increment circuit. Guided by 31. In the memory address data 2j, (K) R is the R address of the address value K,
(K) W indicates the W address of the address value K, and (K) REF indicates the REF address of the address value K. Reference numerals 2h and 2l denote a read address select signal (hereinafter, referred to as SELR) and a write address select signal (hereinafter, referred to as SELW) that are guided to the select circuits 24 and 25, respectively.
An arbitrarily designated address from the register 14 is selected as an address value in which the value from the increment circuit 31 is increased during the "Low" period, and is guided to the R register 26 and the W register 27. 2o, 2p,
2g is a latch pulse for each of the registers 26 to 28, which is generated at the phase of φ ₄ of each cycle, for example, and each register 26 to 28 receives the address increased by the increment circuit 31 or an arbitrary address. 2r, 2s, 2t are R as described above
The address data is led to the register 26, the W register 27, and the REF register 28. For example, (N) _{R of} 2g is an arbitrarily designated R address led from the SAD register 14 to the R register 26, (N +
1) _R is an increment circuit 31 for an arbitrarily designated R address value
The R address is increased by 1.

By the operation of the address generating circuit 33 described above, assuming that the parallel conversion bit number m of SP conversion is 18, the count value of the R counter 17 is also 18 cycles, and the serial D _IN 2u input to the input after SET 2b is 18 bits. As one block unit,
In addition, during the W address period of the memory address 2j, the write address (N) _W, which is arbitrarily specified, is used as the initial address and sequentially (N + 1) _W , (N
+2) _W ... is written in the memory cell array 5. Also, W
If the count cycle of the counter 18 is also set to 18, since 18 bits are read from the memory cell array 15 to the output buffer register 6 in units of one block in the R address period of the memory address 2j, serial D after SET2b is read.
_OUT 2v is an arbitrary read address (N) after 2 blocks
_With ( _R ) as the initial address, (N + 1) _R , (N + 2) _R , ... Are sequentially output. In this case, the serial number specified by (N) _W and (N) _R
Since there is a time difference of 2 blocks between D _IN and D _OUT , for example
By setting the address value offset for 2 blocks between (N) _W and (N) _R , the delay amount of D _OUT can be set by the RES signal, and the delay amount of just one field or one frame can be set easily. Becomes

As described above, in the present invention, each cycle is selected to be 6 clocks as shown in FIG. 2, for example, so that the sum of the R cycle, the W cycle, and the REF cycle in the address generation circuit 33 becomes the bit number m of SP conversion or less. With this, writing of high-speed serial D _IN to the image memory and reading of high-speed serial D _OUT can be performed at the same time, and random access can be made in block units by SAD designation, enabling multi-functionalization.

Another operation example of the embodiment shown in FIG. 1 is shown in FIG. The example of FIG. 3 shows each select circuit 24, 25, 27 for each cycle 3g.
And the phase of the latch pulse of each register 26-28, 30 is different from the example of FIG. This is because in the example of FIG. 2, the serial D _OUT 2v outputs the data of the read address (N) _{R that} is arbitrarily specified after two blocks of the SET 2b, whereas in the example of FIG. 3, D _OUT 3v is the SET 3b. It is possible to output the data of the arbitrary read address (N) _R from one block after. Hereinafter, this will be described in detail.

In FIG. 3, the signals 3a to 3v are the same as the signals 2a to 2v in FIG. 2, respectively, of which the timings 3h to 3v are slightly different. Especially, since the operation timings of the R register 26 and the W register 27 are different depending on the signals of 3k to 3t, this portion will be described first. FIG. 4 is an example of a concrete generation circuit of the latch pulse (RLatch) 3o of the SELR3k and the R register 26, and FIG. 5 is a timing chart showing the operation of the example of FIG. In FIG. 4, 35, 36, 40 are input terminals for each phase clock φ ₅ , φ ₂ , φ ₁ , 37 is an input terminal for RReg5b, 38
Is an input terminal of SET5a, 39 is an R cycle signal 5e, 41 and 42 are output terminals of the latch pulse 5o and SELR5h of the R register 26, respectively.
43 and 44 are flip-flops, 45 to 48 are AND circuits, and 49 is an OR circuit. When SET5a is input, Q of flip-flop 43
₁ Output 5c is set to “High” and then input RReg
It becomes “Low” by 5b, and Q _{2 of the} next flip-flop 44
The output looks like 5d. 5f is this Q ₂ output 5d and R cycle
This is the AND output N ₁ (R) with 5e, and this N ₁ (R) 5f and φ ₁ 5g
As an AND output with and, after SET, SELR for selecting an arbitrarily designated R address is obtained. Further, the latch pulse for fetching the data from the increment circuit 31 to the R register 26 at the normal time is obtained as an AND output N ₃ (R) 5l of RReg 5b and φ ₅ 5k, and the arbitrarily designated R address data is stored in the R register. 26
Latch pulse for taking the A and N ₁ (R) 5f and phi ₂ 5i
Obtained as ND output N ₂ (R) 5j. These two signals N
An OR output 5o of ₂ (R) 5j and N ₃ (R) 5l is supplied as a latch pulse of the R register 26. On the other hand, SELW3l in Fig. 3
The latch pulse 3p of the W register 27 and the latch circuit 3p of the W register 27 have the same configuration as that of FIG. 4, but instead of the RReg5b and the R cycle 5e, the WReg5p and the W cycle 5s are used, and two flip-flops 43 and 44 are used. Q ₁ (W) and Q ₂ (W) outputs are 5g and 5r, respectively
This Q ₂ (W) output 5r and W cycle 5s
N ₁ (W) 5t is obtained as the AND output, and SELW5u is this N
Obtained as an AND output of ₁ (W) 5t and phi ₁ 5 g, is supplied to the select circuit 25. W register 27 latch pulse 5v
Is the same as the latch pulse 5o of R register 26, N ₁ (W) 5t
And WReg5p and φ ₂ 5i, φ ₅ 5h.

By the above operation, the address data held in the registers 26 to 28 become 3r to 3t, respectively, and particularly, in the first R cycle period after SET3b, the arbitrarily designated address
(N) and the incorporation to the R register 26 of _R, taken-the (N) _R the RS
It becomes possible to select by EL3h and lead to the memory address register 3j by the latch pulse 3i, lead to the address decode circuit 32 as R address data, increase the address value by the increment circuit 31 and fetch it to the R register 26 again. . As a result, the data of the arbitrarily designated address from the memory cell array 5 can be read out by one block earlier than the example of FIG. 2, and the data of the arbitrarily designated address can be read out by one block earlier as shown in the serial D _OUT 3v. Can be output.

In this case, by providing an offset for one block in the address value between (N) _W and (N) _R , D _IN and D at the same point
The address value of _OUT can be the same, according to RES3b
It is easy to set the delay amount of D _OUT .

Next, in one embodiment of the present invention shown in FIG.
The operation when the gate is applied to WCLK by using will be described with reference to FIG.

In FIG. 6, 6a is CLK, 6b is CGW, 6c is WCLK obtained as AND output of CGW6b and CLK6a in the gate circuit 16 in FIG. 1, 6d is RES, 6e is RReg, 6f is WReg, 6g is REF
Reg, CLK gating by CGR is not performed in this example, and RCLK is the same as CLK6a. Therefore, RReg6e
And REFReg6g are the same as those in the example of FIG. 3, and the WReg signal 6f is obtained, for example, in 18 clock cycles of WCLK6c after RES6d, so that the generation period of WReg6f is delayed compared to the example of FIG. In this case, each address cycle obtained in the φ ₀ 6h phase becomes 6i. Figure 7 shows each address cycle.
An example of the 6i generation circuit is shown in FIG. In FIG. 7, 50 to 53 are φ ₀ 8d, RReg8a, W shown in FIG. 8, respectively.
Reg8b and REFReg8c input terminals, 54 to 56 are R cycle 8 respectively
Output terminals of h, W cycle 8i and REF cycle 8j, 57 to 59 are set / reset flip-flops (hereinafter referred to as SRFF).
Reference numerals 60 and 61 are inverter circuits, 62 and 63 are AND circuits, 64 to 66 are D-type flip-flops (hereinafter, referred to as DFF), 67 to 69 are edge detection circuits, and SRFF 57 to 59 outputs Q ₁ , The signals shown in 8e to 8g are obtained by Regs 8a to 8c in Q ₂ and Q ₃ , and the inverter circuits 60 and 61 and the AND circuits 62 and 63 are provided with priority in the order of Q ₁ , Q ₂ , and Q ₃ , Lead to D input of each DFF64-66. Each DFF64 ~
By latching the D input signal each in phi ₀ 8d at 66, each R cycle 8h, W cycle 8i, the REF cycle 8j obtained each Q output. Edge detection circuits 67-69 for each cycle
For example, rising edges of 8h to 8j are detected, the detected edge signals 8k to 8o are introduced to reset inputs of SRFFs 57 to 59, respectively, and the Q output of SRFF is reset to take in a new Reg.
By providing the above cycle and generation circuit,
Each cycle signal is assigned in a time-division manner without hitting each other in time. In this way, by allocating the cycle of each address in a time division manner, for example, latch pulse 6k, SELR6o, SELW6p, WSEL6j memory address register 30
And each latch pulse 6 of R register 26 and W register 27
g and 6r are given as shown in FIG. 6, and by these control signals, the address value of the memory address register 30 and the address values of the R register 26 and W register 27 become 6l, 6s and 6t. In this case, D _IN 6u serially input after RES6d
It is written to any appointed constant address (N) _W of the memory cell array 5 at the memory address register 30 address values 6l of (N) _W 18 bits in synchronization with WCLK6c as in FIG example, a serial output D The data of the arbitrarily designated address (N) _R is also led after 1 block like 6v for _OUT . Thus, CG
Be used optionally gated WCLK6c and RCLK in _W signal 6b and CG _R signal, the continuous writing of the D _IN 6u, are possible continuous reading of D _OUT, it may not put to be captured D _IN is written, taken out There is no inconvenience such as not being able to read the desired D _OUT .

FIG. 9 shows an embodiment of the present invention different from FIG.
A feature of the embodiment shown in FIG. 9 is that the arbitrarily designated address from the SAD register 14 is selected at a time by the select circuit 80 together with the address data from the registers 26 to 28. FIG. 10 is a diagram showing the operation of the embodiment shown in FIG. 9, and the operation will be briefly described below with reference to this figure.

In FIG. 9, the components other than the select circuit 80 are the same as those in the embodiment of FIG. In FIG. 10, 10a
Indicates CLK, 10b indicates SET, 10c indicates RReg, 10d indicates φ ₀ , 10e indicates allocation of each cycle, and these are the same as those in the operation diagram of FIG. Reference numerals 10f to 10j are control signals for selection which are guided from the timing generation circuit 34 to the selection circuit 80. For example, when SELR10f is "High", the arbitrarily designated R address from the SAD register 14 is selected, and when SELW10g is "High", the SAD is selected. Register 1
The W address specified by 4 or the like, the R address from the R register 26 when RSEL10h is “High”, the W address from the W register 27 when WSEL10i is “High”, and the REFSEL10j “Hig
When "h", the REF address from the REF register 28 is selected, and the memory address register 3 is selected in the phase of the latch pulse 10h.
Take to 0. 10l indicates the address value fetched in the memory address register 30. 10o to 10g are latch pulses for fetching each address value increased by the increment circuit 31 into each register 26 to 28, and each register 26 to 28 receives 10
The addresses shown in r to 10s are fetched. By the above operation, like the operation example of FIG. 3, the serial D _IN 10u is taken in by the designated address and the serial D _OUT 10 is acquired.
It is possible to take out v.

〔The invention's effect〕

According to the present invention, it is possible to provide an address generation circuit suitable for an image memory that can simultaneously perform high-speed serial data input / output simultaneously and easily realize a random access function to an arbitrarily designated address. In particular, since the circuit scale of the address generation circuit and the increase in the number of input / output terminals can be suppressed, it is suitable as an address generation circuit incorporated in an image memory IC.

[Brief description of drawings]

1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of a circuit operation of the embodiment of FIG. 1, and FIG. 3 is an embodiment of FIG. 5 is a waveform diagram showing another example of the circuit operation of FIG. 4, FIG. 4 is a circuit diagram showing one embodiment of a latch pulse generation circuit for the SELR and R registers supplied to the address generation circuit used in the present invention, and FIG. 4 is a waveform diagram showing an example of the circuit operation of the embodiment of FIG. 4, FIG. 6 is a waveform diagram showing an example of the circuit operation when the WCLK control by CGw is performed in the embodiment of FIG. FIG. 7 is a circuit diagram showing an embodiment of each cycle signal generation circuit for controlling the address generation circuit used in the present invention, and FIG. 8 is a waveform diagram showing an example of the circuit operation of the embodiment of FIG. , Ninth
FIG. 1 is a circuit diagram showing a circuit configuration of another embodiment of the present invention,
FIG. 10 is a waveform chart showing an example of the circuit operation of the embodiment of FIG. Explanation of symbols 3 ... SP converter, 4 ... Input buffer register, 5 ... Memory cell array, 6 ... Output buffer register, 7 ... PS converter, 14 ... SAD register, 15, 16 ... Gate circuit, 17 ... RCLK counter, 18 … WCLK counter, 19… REFCLK counter, 20…
RReg generating circuit, 21 ... WReg generating circuit, 22 ... REFReg generating circuit, 23 ... Timing generating circuit, 24, 25 ... Select circuit, 2
6 ... R register, 27 ... W register, 28 ... REF register, 29
... Select circuit, 30 ... Memory address register, 31 ... Increment circuit, 32 ... Address decode circuit, 33 ... Address generation circuit, 34 ... Address control circuit, 43,44 ... D-type flip-flop, 45-48 ... AND circuit, 49 … OR circuit, 57
~ 59 ... SR type flip-flop, 60, 61 ... Inverter, 62,
63 ... AND circuit, 64-66 ... D-type flip-flop, 67-69
… Edge detection circuit, 80… Select circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09G 5/36 530 E 9177-5G F 9177-5G G 9177-5G (72) Inventor Shigeru Hirahata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Ichio Nakagawa 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Ltd. Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Mitsuo Nakajima, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Kondo, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd., Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Matsumoto Setsuzo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Home Appliances Research Laboratories, Hitachi, Ltd. (72) Inventor Kantoki Oishi Tokyo Metropolitan Elementary School City Josuihon-cho in the 1450 address, Hitachi, Ltd. Musashi factory examiner Tatsuya Yamazaki

Claims (1)

[Claims] 1. A serial-parallel conversion circuit for converting serial input data into parallel data, a parallel-serial conversion circuit for converting parallel data into serial data, and writing of data converted in parallel into a memory cell array. And read means, an address decoder,
An address generation circuit for supplying an address to the address decoder and an address control circuit for controlling the address generation circuit are provided, and in the address generation circuit, at least first to fifth address register circuits and 1
It has one address select circuit and an increment circuit for increasing the address value or a decrement circuit for decreasing the address value. The address select circuit selects at least the first to third register outputs of the five registers in a time division manner. Leading to a fourth register, leading the fourth register output to the address decoder and the increment circuit or decrement circuit, and returning the address value from the increment circuit or decrement circuit to the register selected by the select circuit again, An externally specified arbitrary address is taken into the fifth register, and the arbitrary data taken into the fifth register is led to the first or second register or the fourth register. Image memory.