JPH06100962B2 - Bus control circuit - Google Patents

Description

The present invention relates to a micro program control type bus control circuit used in a data processor.

[Conventional technology]

A micro program control type central processing unit (hereinafter referred to as a CPU) is a system bus interface that controls data transfer between an arithmetic execution unit, an instruction prefetch unit, a cache memory unit, and a main memory or an I / O processor. Data transfer between units, including units, is performed by microinstruction control.

To improve CPU performance, pipeline control and faster clock cycles are being pursued. As a result, it has become difficult to operate all units within one clock cycle due to the delay problem of each unit. Therefore, a method of dividing the operation into two is adopted. That is, various commands created from microinstructions are transmitted and received between the units in the first clock cycle. Then, the execution result of the command is transmitted / received in the next clock cycle. For example, in order to fetch an instruction or an operand from the cache memory unit, a command is sent from the operation execution unit or the prefetch unit to the cache memory unit and a command register in the cache memory unit is set according to a micro instruction at the first clock. The cache memory unit executes this command on the next clock cycle and outputs the instruction or operand data on the bus. The required units capture this data in response to the instructions of the microinstruction.

[Problems to be Solved by the Invention]

When one instruction or operand data transfer extends over two clock cycles or more as described above, it is assumed that micro instruction execution inhibition occurs at the timing when data is output to the bus and the necessary unit fetches it according to the micro instruction. Therefore, no data exists on the bus when execution is resumed. Therefore, data can be transferred by issuing a command in accordance with the microinstruction immediately before the microinstruction whose execution is suppressed. However, the performance of the CPU decreases.

This performance degradation of the CPU can be prevented by providing a backup circuit for the command register and executing it according to the original command register when the execution is restarted. However, if there are multiple units that take more than 2 clocks to transfer data,
Each unit requires a backup circuit for the command register, which has the drawback of increasing the amount of hardware.

An object of the present invention is to eliminate the performance deterioration due to execution resumption even if an execution prohibition signal is generated during data transfer, and to easily realize resumption from execution prohibition without providing a command register backup circuit in each unit. It is to provide such a bus control circuit.

[Means for Solving the Problems]

The bus control circuit of the present invention includes a plurality of units including at least one unit that takes two clocks or more for data transfer, a micro program control unit for controlling the plurality of units, and data transfer between the plurality of units. In a bus control circuit provided in a central processing unit including a bus for carrying out the data, a data storage circuit connected to the bus for storing data from the bus at every clock, and a micro instruction execution level signal sent by the micro program control unit. And a microinstruction execution inhibition signal, and when microinstruction execution inhibition or interrupt processing is executed, an instruction to inhibit data storage to the data storage circuit is issued, and when the microinstruction is reexecuted, the data is stored in the bus to the data storage circuit. Including a data storage control circuit that gives instructions to output .

〔Example〕

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is a bus 1 for transferring data between units in a CPU; a main memory (not shown) or an input / output (hereinafter I / I) connected to the bus 1. O)
An interface unit 2 having an interface signal line 2a for controlling data transfer or communication with a processor (not shown) or the like, an interface circuit 2b and a decoder 2c for decoding microinstructions; a cache circuit 3a connected to the bus 1. A cache memory unit 3 having a command register 3c and a decoder 3b for decoding a command, and storing instruction or operand data; an instruction buffer circuit 4a connected to the bus 1; and this instruction buffer circuit
Prefetch unit 4 having instruction decoder 4b for decoding instructions from 4a and decoder 4d for decoding microinstructions and generating instruction fetch command and control signals for prefetching instructions; registers 5a and 5b connected to bus 1 An operation execution unit 5 for executing an operation having an arithmetic unit (ALU) 5d connected to these registers 5a and 5b and a decoder 5e for decoding a micro instruction and generating a data fetch command and a control signal; a data output control circuit 7a And a data storage control circuit 7 having a storage inhibition control circuit 7b; registers 6a and 6b for controlling the storage operation in response to a data storage inhibition signal provided from the storage inhibition control circuit 7b of this circuit 7 via line 13, and A bus output circuit 6c for controlling data output to the bus 1 in response to the data output instruction signal 14 from the data output control circuit 7a of the circuit 7 is provided. Data storage circuit 6; and control storage for the microprogram (C
S) 8a Microinstruction register 8b for storing microinstructions from this CS8a, microinstruction address circuit 8c for generating an address for CS and interrupt acceptance control circuit 8d, and a microprogram for giving an operation instruction to each unit 2-5. A control unit 8 is included.

In this embodiment, a fetch request for an instruction or operand data created on the basis of a microinstruction in the prefetch unit 4 or the operation execution unit 5 is sent to the cache memory unit 3 via the command line 4c or 5c.

The transmitted command is stored in the command register 3c of the cache memory unit 3 and then decoded by the decoder 3b. In response to the decoding result, the cache circuit 3a sends the data to the bus 1. The commands output from the prefetch unit 4 and the operation execution unit 5 to the cache memory unit 3 in response to the execution inhibition signal (hereinafter referred to as NOEX signal) for inhibiting the execution of the microprogram given via the line 10 are also invalidated. Interface unit 2,
The drive signal when outputting the bus 1 data from the cache memory unit 3, the prefetch unit 4 and the operation execution unit 5 is given from the microinstruction register 8b through the line 9 to the microinstruction or command register.
Decoders 2c and 3 of each unit 2-5 receive commands from 3c
generated by decoding at b, 4d and 5e, line 11a-
Sent to 11d. Data is output to bus 1 in response to a bus drive signal applied via lines 11a-11d.

For example, an interrupt processing request from an I / O processor (not shown) is transmitted as an interrupt signal via the interface unit 2
Sent to 2d. In response to this interrupt signal, the interrupt acceptance control circuit 8d in the microprogram control unit 8 generates an execution level signal which is valid from the start to the end of the interrupt processing and outputs it to the line 12. The execution level signal is a signal indicating that the microprogram is in the process of interrupting. Based on this execution level signal and the NOEX signal given via the line 10, the storage inhibition control circuit 7b generates a data storage inhibition signal and sends it to the line 13 and also produces a data output timing signal to the line 7c. Send out. In response to the data output timing signal and the bus drive signal applied via lines 11a-11d, data output control circuit 7a generates a data output instruction signal and sends it to line 14. In response to the data storage inhibition signal applied via the line 13, the registers 6a and 6b of the data storage circuit 6 inhibit the data acquisition from the bus 1 when the execution of the micro instruction is inhibited or during the interrupt processing. The data stored in the registers 6a and 6b due to this inhibition is output to the bus 1 via the bus output circuit 6c in response to the data output instruction signal applied via the line 14.

When the execution is resumed from the execution inhibited state, the cache memory unit 3 operates according to the contents of the command register 3c regardless of the NOEX signal on the line 10. FIG. 2 shows the bus control operation in this case.

Referring to FIG. 1 and FIG. 2, each unit is a CPU
The operation basically starts on the rising edge of the basic clock signal provided via line 15 (not shown in FIG. 1) of the. In response to an instruction for fetching an instruction or operand data by the microinstruction μ1 of the microprogram 9 stored in the control memory 8a at the S1 stage, the decoder 4d of the prefetch unit 4 or the decoder of the operation execution unit 5
Command C from 5e to cash memory unit 3
_μ1 is output to the command line 4c or 5c. And
At the trailing edge of the S1 stage, that is, the leading edge of the S2 stage, the command C is sent to the command register 3c in the cache memory unit 3.
_μ1 is set. The cache memory unit 3 executes this command C _μ1 in the S2 stage and _{writes the} data on the bus 1.
D1 is output from the cache circuit 3a. At this time, in this embodiment, the NOEX signal on the line 10 is generated between the S2 and S3 stages for some reason, the execution of the micro instruction μ2 in the S2 and S3 stages is suppressed, and the micro instruction μ2 is executed in the S4 stage. It At this time, the data D1 output from the cache memory unit 3 in the S2 stage is the data storage circuit 6
It is loaded into register 6a inside. One of the lines 13 13a
The data storage inhibit signal above is created based on the one clock delayed signal of the NOEX signal on line 10. In response to this signal, the register 6a suppresses the data storage operation from the bus between the S3 stage and the S4 stage. On the S4 stage, the data storage inhibition control circuit 7b detects the NOEX signal on line 10 and the line 12
The data output timing signal is output to the line 7c from the execution level signal indicating that the above interrupt processing is not in progress. In response to the data output timing signal from the line 7c and the drive signal provided via the lines 11a to 11d indicating that all the units are not driving, the data output control circuit 7a
Generates a data output instruction signal for instructing data output to the bus 1 and outputs it to one of the lines 14a. In response to this signal, the bus output circuit 6c outputs the data D1 from the register 6a to the bus 1. Therefore, the data D1 to be output by the cache memory unit 3 at the time of execution of the microinstruction μ2 can be taken into the register 5a in the operation execution unit 5.

When the processing for the interrupt processing request from the outside is accepted, the execution of the micro instruction is suppressed if necessary, and the processing is trapped in the interrupt processing routine. After the processing is completed, the execution is restarted from the original microinstruction, that is, the microinstruction μ2 whose execution is suppressed. These time-based operations are shown in FIG.

Referring to FIGS. 1 and 3, the microinstruction μ1 of the microprogram 9 stored in the microinstruction register 8b in the S1 stage is decoded by the decoder 5e of the operation execution unit 5, and the command C _μ1 changes the command line 5c. The command C _μ1 set in the command register 3c via the decoder 3b is decoded by the decoder 3b and given to the cache circuit 3a. In response to this decoding result, the data D1 is output from the cache circuit 3a to the bus 1. This data D1 is loaded into the register 5a in the operation execution unit 5 by the micro instruction μ2. At the time of this load, an interrupt factor exists and an interrupt signal is sent from the decoder 2c to the interrupt acceptance control circuit 8d via the line 2d. In response to this interrupt signal, the NOEX signal for trapping the microprogram for the interrupt processing is sent from the reception / acceptance control circuit 8d to the line 10, and the microinstruction μ2
Execution is suppressed. In response to this execution inhibition, the register 5a cannot take in the data D1. However, the data D1 is taken into the registers 6a and 6b in the data storage circuit 6. S3
~ S8 stage is executing interrupt processing (micro instruction T0 ~
T4) and the line from the micro program control unit 8
The execution level signal given via 12 indicates that this interrupt processing is being executed. In response to the execution level signal applied via line 12 and the NOEX signal applied via line 10, storage inhibition control circuit 7b sends a data storage inhibition signal to the line group.
A data storage inhibition signal is applied to the register 6a via the line 13a of the line 13. In response to this data storage inhibition signal, the register 6a inhibits the data storage operation from the bus 1 during the interrupt processing. Also, S4, S5, and S6 during interrupt processing
In stage, the command C _T1 decoders 5e in response to the microinstruction T1, command line 5c, is executed in the cache memory unit 3 through the command register 3c and decoder 3b, the data D2 is output to the bus 1 from the cache circuit 3a . When this data D2 is stored in the register 5b in the arithmetic execution unit 5 by the microinstruction T2, the execution of the microinstruction T2 in the S5 stage is suppressed in response to the NOEX signal given via the line 10. The data D2 is about to be taken into the register 6b in the data storage circuit 6. Line 10
In response to the NOEX signal applied via line and the execution level signal applied via line 12, storage inhibition control circuit 7b outputs a data storage inhibition signal to line 13f which is one of line group 13. In response to this data storage inhibit signal, the register
6f suppresses the data storage operation from bus 1 in the S6 stage. When the execution of the interrupt processing program T2 is resumed, in response to the NOEX signal applied via the line 10 and the execution level signal applied via the line 12, the storage inhibition control circuit 7b causes the line 7c to operate.
The data output timing signal is output to. In response to the data output timing signal and the bus drive signal applied via lines 11a-11d, data output control circuit 7a generates a data output instruction signal on line 14f of line group 14.
In response to the data output instruction signal, the data D2 stored in the register 6f is output to the bus 1 and the operation execution unit 5
Can be loaded into register 5b within. After the interrupt processing is completed, the execution is restarted from the micro instruction μ2 at the S9 stage. Run level signal provided via line 12 and line 10
In response to the NOEX signal provided via the storage inhibition control circuit 7b, the storage inhibition control circuit 7b sends an output timing signal to the line 7c. In response to this output timing signal and the bus drive signal for each unit provided via lines 11a-11d, data output control circuit 7a outputs a data output instruction signal to one line 14a of line group 14. In response to the data output instruction signal, the bus output circuit 6c selects the data D1 from the register 6a and outputs it to the bus 1. The data D1 sent to the bus 1 is held by the register 5a in the operation execution unit 5 according to an instruction from the microinstruction μ2.

〔The invention's effect〕

A feature of the present invention is that the data storage circuit 6 having several word registers 6a and 6b connected to the bus 1 inside the central processing unit is provided with a micro controller based on an execution inhibit signal, an execution level signal and a bus drive signal for each unit. When the execution of an instruction is suppressed, the data that should be originally taken into the operation execution circuit 5 is input and stored from the bus 1, and the data is output to the bus 1 when necessary when the execution is restarted. Due to this feature, when one instruction is executed or data is transferred over two clocks, there is an effect that the performance of the CPU is not deteriorated even if the execution inhibition state occurs in the unit that requires data.

Further, the present invention has an effect that it is not necessary to configure a backup circuit such as a command register in each of the units 2 to 5 and the execution can be easily resumed even if the execution at the time of data transfer is suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention; and FIGS. 2 and 3 are diagrams showing an operation of the embodiment of the present invention. In the figure, 1 ... Bus, 2 ... Interface unit, 3 ... Cache memory unit, 4 ... Prefetch unit, 5 ... Operation execution unit, 6 ... Data storage circuit, 7 ... Data storage control circuit, 8 ... ... Microprogram control unit 8.

Claims (1)

[Claims] 1. A plurality of units including at least one unit that requires two or more clocks for data transfer, a micro program control unit for controlling these units, and a bus for transferring data between the plurality of units. A bus control circuit provided in a central processing unit including a data storage circuit connected to the bus for storing data from the bus at every clock, and a micro instruction execution level signal and a micro instruction sent by the micro program control unit. An instruction to monitor the execution inhibition signal, to instruct the data storage circuit to store data when the microinstruction execution is inhibited or to execute an interrupt process, and to output the data to the bus to the data storage circuit when the microinstruction is reexecuted. And a data storage control circuit for performing Bus control circuit to.