JPH06101503B2 - Semiconductor substrate selection method - Google Patents
Semiconductor substrate selection methodInfo
- Publication number
- JPH06101503B2 JPH06101503B2 JP61161367A JP16136786A JPH06101503B2 JP H06101503 B2 JPH06101503 B2 JP H06101503B2 JP 61161367 A JP61161367 A JP 61161367A JP 16136786 A JP16136786 A JP 16136786A JP H06101503 B2 JPH06101503 B2 JP H06101503B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- semiconductor substrate
- layer
- diffusion layer
- sheet resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 239000000758 substrate Substances 0.000 title claims description 49
- 238000010187 selection method Methods 0.000 title description 2
- 238000009792 diffusion process Methods 0.000 claims description 32
- 229910052787 antimony Inorganic materials 0.000 claims description 11
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 11
- 238000011109 contamination Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000007689 inspection Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体基板の選別方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selecting semiconductor substrates.
従来の技術 半導体装置の製造において、アンチモンは拡散定数が小
さく、蒸気圧が低いのでP型半導体基板にN+型埋込層を
形成する場合に良く用いられている。アンチモンを不純
物としてP型半導体基板にN+型埋込層を選択的に形成
後、その上にN型エピタキシャル層を形成し、このN型
エピタキシャル層に素子分離層,ベース層,エミッタ
層,電極を形成することにより半導体装置が形成され
る。この半導体装置の特性を検査すると、コレクタ−エ
ミッタ間の飽和電圧が大きいものが検出される場合があ
る。この原因は、アンチモンによるN+型埋込層形成時に
P型基板からの拡散定数の大きいP型不純物による汚染
があるためである。N+型埋込層形成後、その上にN型エ
ピタキシャル層を形成し、拡散層形成のための熱処理を
行うとN+型埋込層中の拡散定数の大きいP型不純物が拡
散され、N+埋込層とN型エピタキシャル層の間とN+埋込
層の下部にP型拡散層が形成される。このため、アンチ
モンによるN+型埋込層形成後、拡散定数の大きいP型不
純物の汚染の有無を半導体基板で選別する必要がある。2. Description of the Related Art In the manufacture of semiconductor devices, antimony is often used when forming an N + type buried layer on a P type semiconductor substrate because it has a small diffusion constant and a low vapor pressure. After selectively forming an N + type buried layer on a P type semiconductor substrate using antimony as an impurity, an N type epitaxial layer is formed on the N + type buried layer, and an element isolation layer, a base layer, an emitter layer, an electrode are formed on the N type epitaxial layer. A semiconductor device is formed by forming. When the characteristics of this semiconductor device are inspected, the one with a large saturation voltage between the collector and the emitter may be detected. This is because there is contamination by P-type impurities having a large diffusion constant from the P-type substrate when the N + -type buried layer is formed by antimony. After the N + -type buried layer is formed, an N-type epitaxial layer is formed on the N + -type buried layer and heat treatment is performed to form a diffusion layer. A P-type diffusion layer is formed between the + buried layer and the N-type epitaxial layer and below the N + buried layer. Therefore, after forming the N + type buried layer with antimony, it is necessary to select whether or not the P type impurity having a large diffusion constant is contaminated by the semiconductor substrate.
従来の半導体基板の選別方法としては、P型半導体基板
に選択的にアンチモンを拡散させ、N+型埋込層を形成す
る際に、同時にN型半導体基板にアンチモンを拡散させ
N+型拡散層を形成する。前記N型半導体基板を角度研磨
してN+拡散層の下部にP型拡散層が形成されているかを
検査して、前記P型半導体基板の良否を判定する方法が
ある。拡散定数の大きいP型不純物の汚染が有る場合に
は、N型半導体基板は第9図のように、N+型拡散層93の
下部にP型拡散層92が形成される。A conventional method for selecting a semiconductor substrate is to selectively diffuse antimony in a P-type semiconductor substrate and simultaneously diffuse antimony in an N-type semiconductor substrate when forming an N + -type buried layer.
An N + type diffusion layer is formed. There is a method of judging the quality of the P-type semiconductor substrate by angle-polishing the N-type semiconductor substrate and inspecting whether the P-type diffusion layer is formed under the N + diffusion layer. When there is contamination with P-type impurities having a large diffusion constant, the P-type diffusion layer 92 is formed below the N + -type diffusion layer 93 in the N-type semiconductor substrate as shown in FIG.
発明が解決しようとする問題点 しかしながら上記の従来の方法では、半導体基板の研磨
部分を検査するが、半導体基板全面の検査が困難なた
め、検査の精度が十分でないという問題点を有してい
た。Problems to be Solved by the Invention However, in the above-mentioned conventional method, although the polished portion of the semiconductor substrate is inspected, there is a problem that the inspection accuracy is not sufficient because the inspection of the entire surface of the semiconductor substrate is difficult. .
本発明の目的は半導体基板全面の検査が容易に行え、検
査の精度向上を現実できる半導体基板の選別方法を提供
することにある。An object of the present invention is to provide a method of selecting a semiconductor substrate, which can easily inspect the entire surface of the semiconductor substrate and can improve the accuracy of the inspection.
問題点を解決するための手段 この目的を達成するために、本発明の半導体基板の選別
方法では、P型半導体基板に選択的にアンチモンを拡散
させ、N+型拡散層を形成する際に、同時に別のP型半導
体基板の全面にアンチモンを拡散させ、全面にN+型拡散
層を形成する。全面にN+型拡散層を形成したP型半導体
基板のシート抵抗を測定する。さらに前記の全面にN+型
拡散層が形成されたP型半導体基板のみに、その上にエ
ピタキシャル層を形成し、熱処理後、再びシート抵抗を
測定する。シート抵抗の変化により拡散定数の大きいP
型不純物の汚染の有無を検査して、前記の選択的にN+型
拡散層を形成したP型半導体基板の良否を判定するもの
である。Means for Solving the Problems In order to achieve this object, in the method for selecting a semiconductor substrate of the present invention, when antimony is selectively diffused in a P-type semiconductor substrate to form an N + -type diffusion layer, At the same time, antimony is diffused over the entire surface of another P-type semiconductor substrate to form an N + -type diffusion layer over the entire surface. The sheet resistance of the P type semiconductor substrate having the N + type diffusion layer formed on the entire surface is measured. Further, an epitaxial layer is formed only on the P-type semiconductor substrate having the N + -type diffusion layer formed on the entire surface, and after heat treatment, the sheet resistance is measured again. P that has a large diffusion constant due to changes in sheet resistance
Whether or not the P-type semiconductor substrate on which the N + -type diffusion layer is selectively formed is judged to be good or bad by inspecting the presence or absence of contamination of the type impurities.
作用 上記工程による半導体基板の選別方法では、半導体基板
の全面の検査を可能とし、検査精度の向上を実現するこ
とができる。Action The semiconductor substrate selection method according to the above steps enables the entire surface of the semiconductor substrate to be inspected and improves the inspection accuracy.
実施例 以下、本発明を実施例により図面を用いて説明する。第
1図〜第8図は本発明による半導体基板の選別方法の実
施例を示す説明図である。第1図に示すように、N+型埋
込層を選択的に形成すべきP型半導体基板11の表面全面
に熱酸化膜12を形成する。N+型埋込層を形成する部分の
熱酸化膜12を選択的にエッチングし、P型半導体基板11
の一部を露出させる。次に第2図に示すように、前記の
加工されたP型半導体基板11を半導体基板立て治具21に
複数枚立てる。適当な箇所に、選別のために、第3図に
示すP型半導体基板31を配置する。ただし、このP型半
導体基板31には酸化膜のように拡散マスクになるものは
形成されていない。次に、P型半導体基板11,31が配置
された半導体基板立て治具21を、ヒーター22の中の石英
管23に挿入し、ヒーター22を加熱させ送入管24より、ア
ンチモンのガスを石英管23の内部へ流す。これにより、
P型半導体基板11には、第4図に示すように、選択的に
N+型埋込層41が形成される。一方、検査すべきP型半導
体基板31は、第5図に示すように、全面にN+型拡散層51
が形成される。この全面にN+型拡散層51が形成されたP
型半導体基板のシート抵抗を、酸化膜52を除去してから
測定する。次にこの全面にN+型拡散層51が形成されたP
型半導体基板のみに、第6図に示すようにN型エピタキ
シャル層61を形成し、熱処理後、再びシート抵抗を測定
する。アンチモンによるN+型拡散層形成時に拡散定数の
大きいP型不純物の汚染が無い場合には、シート抵抗は
変化しないが、減少する。汚染がある場合には、N+型拡
散層とN型エピタキシャル層の間に、第7図に示すよう
に、P型拡散層71が形成されるため、シート抵抗は大き
く増加する。第8図はシート抵抗と汚染の量との関係を
示すもので、両者は比較関係がある。このP型半導体基
板のシート抵抗が増加した場合には、半導体基板立て治
具21に配置されたP型半導体基板11は全て汚染が有り、
不良品と判定する。このシート抵抗が変化しないか、減
少する場合には、汚染が無く、良品と判定し、その後の
工程続行に供する。EXAMPLES Hereinafter, the present invention will be described by way of examples with reference to the drawings. 1 to 8 are explanatory views showing an embodiment of a method for selecting a semiconductor substrate according to the present invention. As shown in FIG. 1, a thermal oxide film 12 is formed on the entire surface of a P type semiconductor substrate 11 on which an N + type buried layer is to be selectively formed. The P-type semiconductor substrate 11 is formed by selectively etching the thermal oxide film 12 in the portion forming the N + -type buried layer.
Expose part of. Next, as shown in FIG. 2, a plurality of the processed P-type semiconductor substrates 11 are erected on a semiconductor substrate erecting jig 21. The P-type semiconductor substrate 31 shown in FIG. 3 is arranged at an appropriate place for selection. However, the P-type semiconductor substrate 31 is not formed with a diffusion mask such as an oxide film. Next, the semiconductor substrate stand jig 21 on which the P-type semiconductor substrates 11 and 31 are arranged is inserted into the quartz tube 23 in the heater 22, the heater 22 is heated, and the antimony gas is fed into the quartz tube 23 through the inlet tube 24. Pour into tube 23. This allows
As shown in FIG. 4, the P-type semiconductor substrate 11 is selectively
An N + type buried layer 41 is formed. On the other hand, as shown in FIG. 5, the P-type semiconductor substrate 31 to be inspected has an N + -type diffusion layer 51 over the entire surface.
Is formed. P with the N + type diffusion layer 51 formed on the entire surface
The sheet resistance of the type semiconductor substrate is measured after removing the oxide film 52. Next, P with the N + type diffusion layer 51 formed on the entire surface
The N-type epitaxial layer 61 is formed only on the type semiconductor substrate as shown in FIG. 6, and after heat treatment, the sheet resistance is measured again. When the N + type diffusion layer is formed by antimony and the P type impurities having a large diffusion constant are not contaminated, the sheet resistance does not change but decreases. When there is contamination, a P type diffusion layer 71 is formed between the N + type diffusion layer and the N type epitaxial layer, as shown in FIG. 7, so that the sheet resistance is greatly increased. FIG. 8 shows the relationship between the sheet resistance and the amount of contamination, and both have a comparative relationship. When the sheet resistance of the P-type semiconductor substrate increases, the P-type semiconductor substrate 11 arranged on the semiconductor substrate stand jig 21 is all contaminated,
Judge as defective. If the sheet resistance does not change or decreases, it is determined that there is no contamination and the product is non-defective, and the subsequent process is continued.
発明の効果 以上のように、本実施例にれば、検査すべき半導体基板
を研磨せずに、シート抵抗を測定することにより汚染を
検査するので、半導体基板の全面の検査が容易に可能と
なり、検査精度が向上する。さらに、拡散定数の大きい
P型不純物の汚染の量により、P型拡散層の厚みが変わ
り、シート抵抗も変わるので、そのシート抵抗の変化量
から、汚染の量が測定可能となり、これによって、工程
途上で良否判別ができ、半導体装置の製造性を向上する
ことができる。As described above, according to the present embodiment, since the contamination is inspected by measuring the sheet resistance without polishing the semiconductor substrate to be inspected, it is possible to easily inspect the entire surface of the semiconductor substrate. , The inspection accuracy is improved. Furthermore, since the thickness of the P-type diffusion layer changes and the sheet resistance also changes depending on the amount of contamination of P-type impurities having a large diffusion constant, the amount of contamination can be measured from the amount of change in the sheet resistance. The quality can be determined on the way and the manufacturability of the semiconductor device can be improved.
第1図〜第8図は本発明の一実施例を説明するための概
要図、第9図は従来の方法を説明するための断面図であ
る。 11,31……P型半導体基板、12,52……熱酸化膜、41……
N+型埋込層、51……N+型拡散層、61……N型エピタキシ
ャル層、71……P型拡散層。1 to 8 are schematic views for explaining an embodiment of the present invention, and FIG. 9 is a sectional view for explaining a conventional method. 11,31 …… P-type semiconductor substrate, 12,52 …… Thermal oxide film, 41 ……
N + type buried layer, 51 ... N + type diffusion layer, 61 ... N type epitaxial layer, 71 ... P type diffusion layer.
Claims (1)
2のP型半導体基板にN型拡散層を形成し、前記第2の
P型半導体基板上のN型拡散層のシート抵抗を測定する
とともに、さらに前記第2のP型半導体基板上のN型拡
散層の上にN型のエピタキシャル層を形成し、同エピタ
キシャル層のシート抵抗を測定することにより同P型半
導体基板からのP型不純物汚染度を検査して、前記の半
導体基板の良否を判定することを特徴とする半導体基板
の選別方法。1. An N-type diffusion layer is simultaneously formed on first and second P-type semiconductor substrates using antimony as an impurity, and a sheet resistance of the N-type diffusion layer on the second P-type semiconductor substrate is measured. At the same time, an N-type epitaxial layer is formed on the N-type diffusion layer on the second P-type semiconductor substrate, and the sheet resistance of the epitaxial layer is measured to obtain a P-type impurity from the P-type semiconductor substrate. A method of selecting a semiconductor substrate, characterized by inspecting the degree of contamination to determine the quality of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161367A JPH06101503B2 (en) | 1986-07-09 | 1986-07-09 | Semiconductor substrate selection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161367A JPH06101503B2 (en) | 1986-07-09 | 1986-07-09 | Semiconductor substrate selection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6317539A JPS6317539A (en) | 1988-01-25 |
| JPH06101503B2 true JPH06101503B2 (en) | 1994-12-12 |
Family
ID=15733738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61161367A Expired - Lifetime JPH06101503B2 (en) | 1986-07-09 | 1986-07-09 | Semiconductor substrate selection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101503B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5444655B2 (en) * | 2008-07-30 | 2014-03-19 | 株式会社Sumco | Manufacturing method of semiconductor substrate |
-
1986
- 1986-07-09 JP JP61161367A patent/JPH06101503B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6317539A (en) | 1988-01-25 |
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