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JPH0666369B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0666369B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0666369B2
JPH0666369B2 JP62006071A JP607187A JPH0666369B2 JP H0666369 B2 JPH0666369 B2 JP H0666369B2 JP 62006071 A JP62006071 A JP 62006071A JP 607187 A JP607187 A JP 607187A JP H0666369 B2 JPH0666369 B2 JP H0666369B2
Authority
JP
Japan
Prior art keywords
electrode
ohmic contact
semiconductor device
junction
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62006071A
Other languages
Japanese (ja)
Other versions
JPS63175439A (en
Inventor
欣三 田尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62006071A priority Critical patent/JPH0666369B2/en
Publication of JPS63175439A publication Critical patent/JPS63175439A/en
Publication of JPH0666369B2 publication Critical patent/JPH0666369B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置のチップ表面電極形成時のオーミ
ックコンタクト(ohmic contact)に関するもので、光
エネルギーを利用した低電流(例えば数nA)値の変化
でオーミックコンタクトの良否を非破壊的に判定する方
法に係るものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to an ohmic contact when forming a chip surface electrode of a semiconductor device. For example, the present invention relates to a method of nondestructively determining the quality of ohmic contact by a change in value of several nA.

(従来の技術) 半導体装置の製造に当たり、チップ表面電極形成時に活
性領域シリコン基板面と表面電極とのオーミックコンタ
クト性の一般的な従来の評価方法について、PN接合ダ
イオードのアノード表面電極の評価方法を1例として以
下説明する。第3図はPN接合ダイオードの断面図であ
る。この場合、アノード側電極端子1はチップの一方の
主面から取り出し、カソード側電極端子2は他方の主面
から取り出し、カソード表面電極のオーミックコンタク
トは説明の便宜上正常なものとする。
(Prior Art) In manufacturing a semiconductor device, a conventional conventional evaluation method of ohmic contact between an active region silicon substrate surface and a surface electrode at the time of forming a chip surface electrode is described below. An example will be described below. FIG. 3 is a sectional view of a PN junction diode. In this case, the anode side electrode terminal 1 is taken out from one main surface of the chip, the cathode side electrode terminal 2 is taken out from the other main surface, and the ohmic contact of the cathode surface electrode is normal for convenience of explanation.

第4図に基づき表面電極形成方法の1例の概要を説明す
る。同図(a)において先ず活性領域であるP拡散層
3の表面上にPEP(Photo Engraving Process)方で
電極取り出し開口部4を形成する。次に一般的な電極材
料であるアルミニウム(Al)を蒸着法でチップの主面
に被着した後、PEP法で表面電極5を形成する。この
場合電極取り出し開口部に露出する活性領域面6と表面
電極5のAl面との良好なオーミックコンタクトを得る
ために500℃前後の温度で数分間熱処理(アルミシンタ
ー処理)を施す方法がとられる。この場合電極取り出し
開口部の活性領域面6にエッチング不完全により薄膜
(主に厚さ300Å以下のSiO膜)が残っていると
き、或いはアルミ蒸着時の条件不適当等のとき、これが
原因でシンター処理後正常なオーミックコンタクトが得
られず、ダイオードの順方向特性(V−I特性)が
不具合となる。
An outline of an example of the surface electrode forming method will be described with reference to FIG. In FIG. 3A, first, an electrode lead-out opening 4 is formed on the surface of the P + diffusion layer 3 which is an active region by PEP (Photo Engraving Process). Next, after depositing aluminum (Al), which is a general electrode material, on the main surface of the chip by vapor deposition, the surface electrode 5 is formed by PEP. In this case, in order to obtain a good ohmic contact between the active region surface 6 exposed in the electrode extraction opening and the Al surface of the surface electrode 5, a method of performing heat treatment (aluminum sintering treatment) at a temperature of about 500 ° C. for several minutes is used. . In this case, when a thin film (mainly a SiO 2 film with a thickness of 300 Å or less) remains on the active region surface 6 of the electrode extraction opening due to incomplete etching, or when the conditions for aluminum deposition are inappropriate, this is the cause. normal ohmic contact after sintering process can not be obtained, the forward characteristics (V F -I F characteristics) of the diode becomes defect.

(A)ダイオードの順方向特性の評価方法として一般的
には、第3図のアノード端子1とカソード端子2との間
に順方向バイアス電圧を印加し、第4図(b)に示すよ
うなV−I波形をカーブトレーサーで観察するが、
オーミックコンタクトが正常な場合と不具合な場合を判
別するためには数百mAないし数Aの順方向電流I
流し、その時の順方向電圧Vの差で判定する。すなわ
ち同図(b)のV−I波形で曲線mは正常品、曲線
nは不具合の特性を示す。この場合数百mAないし数A
のIを必要とするため、第4図(c)に示すようにパ
ターン測定針7およびウエーハ裏面とステージ8との接
触部での電圧降下を招き、正常な測定が困難となる。特
に高速自動測定は、例えばケルビン法等の測定方法の改
善を行ってもパターンの大きさ等の制約もあり正常な測
定が難しい。
(A) In general, as a method for evaluating the forward characteristic of a diode, a forward bias voltage is applied between the anode terminal 1 and the cathode terminal 2 in FIG. 3, and as shown in FIG. 4 (b). While observing the V F -I F waveform curve tracer,
In order to determine whether the ohmic contact is normal or defective, a forward current I F of several hundred mA or several A is passed and the difference in the forward voltage V F at that time is used for the determination. That V F -I F waveform curve m is a normal product, curve n in (b) shows a defect characteristics. In this case, several hundred mA or several A
For requiring I F, it causes a voltage drop at the contact portion between the pattern measurement needle 7 and the wafer rear surface and the stage 8 as shown in FIG. 4 (c), it is difficult to normal measurement. Particularly in high-speed automatic measurement, even if the measurement method such as the Kelvin method is improved, it is difficult to perform normal measurement due to the restrictions such as the size of the pattern.

オーミックコンタクト性の電気的な評価は、上記のV
−I波形観測法以外にも抵抗法等があるが、直接チッ
プ測定でなく一長一短を有する。
The electrical evaluation of ohmic contact property is based on the above V F
Besides -I F waveform observation method is resistance method or the like, but have advantages and disadvantages rather than direct chip measurement.

(B)オーミックコンタクト性の別の評価方法として、
アルミシンター処理を施した後、表面電極であるアルミ
ニウムをエッチング法で除去し、表面を顕微鏡で観察す
る方法がある。第4図(d)は、オーミックコンタクト
が正常時の表面状態の断面を模式的に示したもので、9
はシンター層と呼ばれるアルミ・シリコン反応層であ
る。不具合時にはシンター層が少なくなっている。この
方法は正常時と不具合時の判別はできても、破壊試験で
あり全数評価は不可能である。
(B) As another evaluation method of ohmic contact property,
After performing the aluminum sintering treatment, there is a method in which aluminum as a surface electrode is removed by an etching method and the surface is observed with a microscope. FIG. 4 (d) schematically shows a cross section of the surface state when the ohmic contact is normal.
Is an aluminum-silicon reaction layer called a sinter layer. When there is a problem, the sintering layer is low. Although this method can distinguish between normal and defective, it is a destructive test and total evaluation is impossible.

(発明が解決しようとする問題点) PN接合を有する半導体装置の表面電極形成時のオーミ
ックコンタクト性の評価方法として前記(A)項の電気
的特性評価(V法)及び(B)項の科学反応による表
面状態の変化を観察する方法について説明したが、いず
れも次のような問題点がある。
(Invention Problems to Solved) wherein (A) Electrical characterization of the term as an ohmic contact property evaluation method when the surface electrode forming a semiconductor device having a PN junction (V F method) and (B) of claim The methods for observing changes in the surface state due to scientific reactions have been explained, but all have the following problems.

(A)電気的特性評価(V法) PN接合に数百mAないし数Aの順方向電流Iを流さ
ないとオーミックコンタクトの正常時と不具合時の判別
が困難であり、この場合パターン測定針の太さ大きさは
表面電極によって制約され、又他方の電極(例えばカソ
ード側ウエーハ裏面電極()と測定器(ステージ)との
接触状態で電圧低下を招き正確な測定が困難となる。
(A) an electrical characterization (V F method) difficult to discriminate the normal state and defect ohmic contact when not conduct forward current I F hundreds mA to several A to the PN junction, this pattern measurement The thickness of the needle is restricted by the front surface electrode, and a voltage drop occurs in the contact state between the other electrode (for example, the cathode side wafer back surface electrode () and the measuring device (stage), which makes accurate measurement difficult.

(B)化学反応による表面状態の変化を観察する方法。(B) A method of observing a change in surface state due to a chemical reaction.

シンター処理後、表面電極であるアルミニウム化学的に
エッチングした後、開口部の顕微鏡観察で、オーミック
コンタクトの正常時と不具合時の判別は正確に判別でき
るが、破壊試験であり、生産上全数評価はできない。
After the sinter treatment, after chemically etching aluminum that is the surface electrode, it is possible to accurately distinguish between normal and defective ohmic contacts by observing the openings with a microscope, but this is a destructive test, and the total evaluation in production is Can not.

本発明の目的は、PN接合を有する半導体装置の表面電
極のオーミックコンタクト性を評価する場合の前記問題
点を解決し、正確且つ非破壊的に全数評価が素子製造工
程において容易に高速に実現でき、それにより後工程の
加工損失を減少できる半導体装置の製造方法を提供する
ことである。
The object of the present invention is to solve the above-mentioned problems in the case of evaluating the ohmic contact property of the surface electrode of a semiconductor device having a PN junction, and to realize accurate and nondestructive 100% evaluation easily and at high speed in the element manufacturing process. Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the processing loss in the subsequent process.

[発明の構成] (問題点を解決するための手段と作用) 本発明は、PN接合を有する半導体基板の活性領域面
に、オーム接触する表面電極のオーミックコンタクト性
を素子製造工程において評価する方法であって、前記表
面電極に測定器の測定入力端子を接触した前記PN接合
に低い逆方向バイアス電圧を印加した状態で、前記基板
面に光を照射した時の測定入力端子を流れる微少光電流
を求め、例えば正常なオーミックコンタクトが得られて
いるときは数nA程度の光電流が流れ、不具合の場合は
その程度により光電流値が減少し、完全不具合の場合は
光照射を行っても光電流が流れないなど、その変化量を
利用してオーム接触に良否を判別する半導体装置の製造
方法である。
[Configuration of Invention] (Means and Actions for Solving Problems) The present invention is a method for evaluating ohmic contact property of a surface electrode in ohmic contact with an active region surface of a semiconductor substrate having a PN junction in a device manufacturing process. In the state where a low reverse bias voltage is applied to the PN junction in which the measurement input terminal of the measuring device is in contact with the surface electrode, a small photocurrent flowing through the measurement input terminal when light is irradiated on the substrate surface. For example, when a normal ohmic contact is obtained, a photocurrent of about several nA flows, and in the case of a defect, the photocurrent value decreases depending on the level. This is a method of manufacturing a semiconductor device in which whether the ohmic contact is good or bad is determined by utilizing the amount of change in that no current flows.

本発明は基板に光照射をしたとき、PN接合部及びその
近傍領域に光励起によるキャリアが発生し、それによる
微少電流が表面電極のオーミックコンタクト性によって
変化する現象を利用するものである。
The present invention utilizes the phenomenon that when a substrate is irradiated with light, carriers are photoexcited in the PN junction and a region in the vicinity of the PN junction, and the resulting minute current changes depending on the ohmic contact property of the surface electrode.

(実施例) 本発明の実施例を半導体装置の基本であるPN接合ダイ
オードの1例について説明する。第1図(a)はPN接
合ダイオードの断面図である。N型半導体基板10は、
これとP拡散層13(活性領域)とによるPN接合1
4を有し、基板10の表面には保護用酸化膜(SiO
膜)11にPEP技術により電極取り出し開口部が設け
られる。開口部に露出する活性領域面16とオーム接触
をするアルミ表面電極15が設けられる。その後表面電
極15はアルミニウムのシンター処理が施される。
(Example) An example of the PN junction diode which is the basis of the semiconductor device will be described as an example of the present invention. FIG. 1A is a sectional view of a PN junction diode. The N-type semiconductor substrate 10 is
PN junction 1 by this and P + diffusion layer 13 (active region)
4 and a protective oxide film (SiO 2
An electrode extraction opening is provided in the film 11 by the PEP technique. An aluminum surface electrode 15 is provided which makes ohmic contact with the active area surface 16 exposed in the opening. Thereafter, the surface electrode 15 is subjected to aluminum sintering treatment.

次に第1図(b)を参照し、この表面電極のオーミック
コンタクト性の評価方法について述べる。前記シンター
処理済のウエーハを測定器のステージ18に置き、パタ
ーン測定針(測定入力端子)17を表面電極15に接触
し、測定器をオンしてPN接合に逆バイアス電圧(0に
近い低電圧)を印加する。即ちステージ18の電位を基
準(0V)とすればアノード側の電位は不電位となる。
この状態で測定針17を流れる電流Iは、照明の無い
場合では殆ど0(0.1nA以下)である。次にウエーハ表
面(アノード側)にスポットライト19を照射すると第
1図(c)のQ点で示すように光電流として10nA以
上の電流Iが流れる。この場合は表面電極15のオー
ミックコンタクトは正常である。但しステージ18とウ
エーハとのオーミックコンタクトは正常とする。表面電
極15のオーミックコンタクトが完全不具合時には、同
図のQ点で示すように殆ど電流は流れず、光照射によ
る電流変化は起こらない。即ち照射する光エネルギーが
一定であれば、オーミックコンタクトの不具合の程度に
よりIは減少しオーミックコンタクト性の評価はでき
る。
Next, with reference to FIG. 1 (b), a method for evaluating the ohmic contact property of the surface electrode will be described. The wafer subjected to the sintering treatment is placed on the stage 18 of the measuring instrument, the pattern measuring needle (measurement input terminal) 17 is brought into contact with the surface electrode 15, and the measuring instrument is turned on to reverse bias voltage (low voltage close to 0 to the PN junction). ) Is applied. That is, if the potential of the stage 18 is set to the reference (0 V), the potential on the anode side becomes a non-potential.
The current I R flowing through the measuring needle 17 in this state is almost 0 (0.1 nA or less) without illumination. Then the wafer surface (anode side) to 10nA or more current I R flows photocurrent as shown by Q 1 point of FIG. 1 is irradiated with a spotlight 19 (c). In this case, the ohmic contact of the surface electrode 15 is normal. However, the ohmic contact between the stage 18 and the wafer is normal. When the ohmic contact of the surface electrode 15 is completely defective, almost no current flows as indicated by the point Q 2 in the figure, and no current change due to light irradiation occurs. That is, if the irradiation light energy is constant, I R decreases depending on the degree of failure of ohmic contact, and the ohmic contact property can be evaluated.

以上主として表面電極15に着目して説明したが、更に
基板10の下面(図面上)にカソード表面電極12が形
成されたダイオードの評価についても同様に可能であ
る。即ち両電極12,15がともに正常なら光電流I
はQ点、いずれかが完全不具合のときはQ点を示
す。中間値の場合には、あらかじめ同種素子の複数枚の
ウエーハ又はペレットについて試行を行い、その結果を
参照していずれの電極が不具合でどの程度かの判別がで
きる。
Although the above description has been focused mainly on the surface electrode 15, the diode having the cathode surface electrode 12 formed on the lower surface (on the drawing) of the substrate 10 can also be evaluated in the same manner. That photocurrent I R if both electrodes 12 and 15 are both normal
Indicates Q 1 point, and Q 2 point when either of them is completely defective. In the case of an intermediate value, trials are performed in advance for a plurality of wafers or pellets of the same type of element, and it is possible to determine which electrode is defective and to what extent by referring to the result.

第2図は本発明の製造方法をエピタキシャル二重拡散型
トランジスタに適用した他の実施例である。エピタキシ
ャルウエーハ20にエミッタ拡散層23、ベース拡散層
27が形成され、基板の主表面に酸化膜21、エミッタ
電極25及びベース電極26、基板の他の主表面にコレ
クタ電極22が設けられる。同図(a)はエミッタ電極
25のオーム接触の良否を判別する方法を示すものであ
る。ウエーハ20を測定器の一方の測定入力端子である
ステージ18上に置き、他方の測定入力端子であるパタ
ーン測定針17をエミッタ電極25に接触し、測定器を
オンしてエミッタ接合24Eに逆バイアス電圧を印加
し、基板面に光を照射しないときの測定針17を流れる
電流即ちリーク電流を求め、次に基板面にスポットライ
ト19を照射したときの電流を求め、その差の校正され
た電流値により、エミッタ電極25のオーム接触の良否
を第1実施例同様判別する。前記リーク電流が小さく無
視できる場合には校正する必要はない。又ベース電極2
6のオーム接触の良否を判別する場合には同図(a)に
おいてパターン測定針17をベース電極26に接触し、
測定器の測定入力端子の極性を変更し即ちコレクタ接合
24Cが逆バイアスされるようにしたのち前記と同様の
方法で測定すればよい。
FIG. 2 shows another embodiment in which the manufacturing method of the present invention is applied to an epitaxial double diffusion type transistor. An emitter diffusion layer 23 and a base diffusion layer 27 are formed on the epitaxial wafer 20, an oxide film 21, an emitter electrode 25 and a base electrode 26 are provided on the main surface of the substrate, and a collector electrode 22 is provided on the other main surface of the substrate. FIG. 9A shows a method for determining the quality of ohmic contact of the emitter electrode 25. The wafer 20 is placed on the stage 18 which is one measurement input terminal of the measuring instrument, the pattern measuring needle 17 which is the other measurement input terminal is brought into contact with the emitter electrode 25, the measuring instrument is turned on and the emitter junction 24E is reverse biased. The current flowing through the measuring needle 17 when the voltage is applied and the substrate surface is not irradiated with light, that is, the leak current is obtained, and then the current when the spotlight 19 is irradiated on the substrate surface is obtained, and the difference is calibrated current. Based on the value, the quality of the ohmic contact of the emitter electrode 25 is determined as in the first embodiment. If the leakage current is small and can be ignored, it is not necessary to calibrate. Also base electrode 2
In order to determine the quality of the ohmic contact of No. 6, the pattern measuring needle 17 is brought into contact with the base electrode 26 in FIG.
The polarity of the measurement input terminal of the measuring instrument is changed, that is, the collector junction 24C is reverse-biased, and then the measurement may be performed by the same method as described above.

同図(b)は、測定入力端子がパターン測定針37,3
8から成る測定器を使用して、エミッタ電極25とベー
ス電極26とのオーム接触の良否を判別する方法を示す
もので、エミッタ接合24Eに逆バイアス電圧を加え、
パターン測定針37又は38を流れる電流値を求める。
In the same figure (b), the measurement input terminals are the pattern measuring needles 37, 3
8 shows a method of determining whether the ohmic contact between the emitter electrode 25 and the base electrode 26 is good or bad by using the measuring instrument composed of 8; applying a reverse bias voltage to the emitter junction 24E,
The value of the current flowing through the pattern measuring needle 37 or 38 is obtained.

特許請求の範囲第2項記載の通り低電圧逆方向バイアス
値は、10Vを越えないことが望ましいが、こバイアス値
は、素子のPN接合の逆耐圧値によって制限されると共
に基板表面のリーク電流等の部分導通の危険を少なくす
るためできるだけ0に近い低電圧とすることが好まし
く、この低電圧値は試行により決定する。
It is desirable that the low voltage reverse bias value does not exceed 10 V as described in claim 2, but this bias value is limited by the reverse breakdown voltage value of the PN junction of the device and the leakage current on the substrate surface. In order to reduce the risk of partial conduction such as, it is preferable to set the low voltage as close to 0 as possible, and this low voltage value is determined by trial.

又光エネルギーに関しては測定系の低電流検出感度や基
板の光励起効率の周波数特性或いは基板内への光の入射
程度等を考慮して決められるが、特別な照射をしない場
合即ち一般照明(又はスポットライト)の場合には照度
100lxないし1000lxが望ましく、その時の測定器の感度
は数nA程度が必要である。又逆バイアスを印加するP
N接合は基板面から浅く、PN接合を形成する半導体領
域の少なくとも一方が基板表面層にあるものが好まし
い。
The light energy can be determined in consideration of the low current detection sensitivity of the measurement system, the frequency characteristics of the photoexcitation efficiency of the substrate, or the degree of light incident on the substrate, but when no special irradiation is performed, that is, general illumination (or spot) Illuminance in case of (light)
100 lx to 1000 lx is desirable, and the sensitivity of the measuring instrument at that time needs to be several nA. In addition, P to apply reverse bias
The N-junction is preferably shallow from the substrate surface and at least one of the semiconductor regions forming the PN junction is in the substrate surface layer.

尚上記実施例ではシンター処理後の状態で説明したが、
電極形成直後にオーミックコンタクト性の評価をするこ
とは勿論できるし、電極取り出し開口部形成後露出する
活性領域面(例えば第1図(a)の16)の状態の評価
も本発明の方法により可能なことを確認した。
In the above embodiment, the description has been made after the sintering process,
Of course, the ohmic contact property can be evaluated immediately after the electrode is formed, and the state of the active region surface (for example, 16 in FIG. 1A) exposed after forming the electrode extraction opening can also be evaluated by the method of the present invention. I confirmed that.

[発明の効果] 以上述べたようにチップ表面電極形成時に、基板の活性
領域面と表面電極とのオーミックコンタクト性の従来の
評価方法では、ウエーハ素子状態での不具合時の判別が
完全でなく、組立加工後で不具合が発見される割合が高
く、加工損失となっていた。
[Advantages of the Invention] As described above, in the conventional evaluation method of the ohmic contact property between the active region surface of the substrate and the surface electrode at the time of forming the chip surface electrode, the determination at the time of failure in the wafer element state is not complete, There was a high rate that defects were discovered after assembly processing, resulting in processing loss.

本発明の表面電極のオーミックコンタクト性を評価する
方法は、微少光電流を使用するので従来の大電流による
不正確さはなくなり、ウエーハ素子状態で正確且つ非破
壊的な全数評価が容易に高速に可能となり、組立加工以
前に不具合品を発見することができ、後工程の加工損失
を減少し、歩留り及び信頼性が向上した。
Since the method for evaluating the ohmic contact property of the surface electrode of the present invention uses a small photocurrent, the inaccuracy caused by a large current in the related art is eliminated, and accurate and nondestructive total evaluation in a wafer element state is easily and quickly performed. It is possible to detect defective products before assembly processing, reduce processing loss in the post process, and improve yield and reliability.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)は本発明の説明に用いるPN接合ダイオー
ドの断面図、同図(b)は本発明の製造方法の説明図、
同図(c)はオーム接触の良否を示す電流分布図、第2
図は本発明の製造方法の他の実施例の説明図、第3図は
従来の製造方法の説明に用いるPN接合ダイオードの電
極取り出し図、第4図(a)は従来の製造方法の説明に
用いるPN接合ダイオードの断面図、同図(b)は同図
(a)のダイオードのV−I(順方向)特性図、同
図(c)及び(d)は従来の製造方法の説明図である。 3,13……P拡散層、4……電極取り出し開口部、
5,15……アノード表面電極、6,16……活性領域
面、7,17,37,38……測定入力端子(パターン
測定針)、8,18……測定入力端子(ステージ)、1
0……半導体基板、14,24E,24C……PN接
合、19……スポットライト、20……半導体基板(エ
ピタキシャルウエーハ)、21……酸化膜(Si
)、23……エミッタ拡散層、25……エミッタ電
極、26……ベース電極、27……ベース拡散層。
1A is a sectional view of a PN junction diode used for explaining the present invention, FIG. 1B is an explanatory view of a manufacturing method of the present invention,
FIG. 2C is a current distribution diagram showing the quality of ohmic contact, the second
FIG. 4 is an explanatory view of another embodiment of the manufacturing method of the present invention, FIG. 3 is an electrode lead-out drawing of a PN junction diode used for explaining the conventional manufacturing method, and FIG. 4 (a) is an explanation of the conventional manufacturing method. sectional view of a PN junction diode is used, FIG. (b) is V F -I F (forward) characteristic diagram of a diode of FIG (a), FIG. (c) and (d) a description of a conventional manufacturing method It is a figure. 3, 13 ... P + diffusion layer, 4 ... Electrode extraction opening,
5, 15 ... Anode surface electrode, 6, 16 ... Active region surface, 7, 17, 37, 38 ... Measurement input terminal (pattern measuring needle), 8, 18 ... Measurement input terminal (stage), 1
0 ... Semiconductor substrate, 14, 24E, 24C ... PN junction, 19 ... Spotlight, 20 ... Semiconductor substrate (epitaxial wafer), 21 ... Oxide film (Si
O 2 ), 23 ... Emitter diffusion layer, 25 ... Emitter electrode, 26 ... Base electrode, 27 ... Base diffusion layer.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】PN接合を有する半導体基板の活性領域面
にこれとオーム接触をする表面電極を形成する工程と、
前記表面電極に測定器の測定入力端子を接触して前記P
N接合に低電圧の逆方向バイアスを印加し、前記基板面
に光を照射したときの前記測定入力端子を流れる電流値
を求め、前記オーム接触の良否を測定する工程とを含む
ことを特徴とする半導体装置の製造方法。
1. A step of forming a surface electrode in ohmic contact with an active region surface of a semiconductor substrate having a PN junction,
When the measurement input terminal of the measuring instrument is brought into contact with the surface electrode, the P
Applying a low-voltage reverse bias to the N-junction, determining a current value flowing through the measurement input terminal when the substrate surface is irradiated with light, and measuring the quality of the ohmic contact. Of manufacturing a semiconductor device.
【請求項2】低電圧逆方向バイアス値が10Vを越えない
特許請求の範囲第1項記載の半導体装置の製造方法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein the low voltage reverse bias value does not exceed 10V.
【請求項3】照射する光の照度が100lxないし1000lxで
ある特許請求の範囲第1項又は第2項記載の半導体装置
の製造方法。
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the illuminance of the irradiation light is 100 lx to 1000 lx.
【請求項4】基板面に光を照射したときの前記電流値
を、基板面に光を照射しないときの前記測定入力端子を
流れる電流値との差とする特許請求の範囲第1項ないし
第3項いずれか記載の半導体装置の製造方法。
4. The method according to claim 1, wherein the current value when the substrate surface is irradiated with light is a difference from the current value which flows through the measurement input terminal when the substrate surface is not irradiated with light. 4. The method for manufacturing a semiconductor device according to any one of 3 above.
JP62006071A 1987-01-16 1987-01-16 Method for manufacturing semiconductor device Expired - Fee Related JPH0666369B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62006071A JPH0666369B2 (en) 1987-01-16 1987-01-16 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62006071A JPH0666369B2 (en) 1987-01-16 1987-01-16 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63175439A JPS63175439A (en) 1988-07-19
JPH0666369B2 true JPH0666369B2 (en) 1994-08-24

Family

ID=11628344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62006071A Expired - Fee Related JPH0666369B2 (en) 1987-01-16 1987-01-16 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0666369B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54102977A (en) * 1978-01-31 1979-08-13 Nec Home Electronics Ltd Test method for semiconductor element
JPS58116743A (en) * 1981-12-25 1983-07-12 Toshiba Corp Inspecting device for bonding

Also Published As

Publication number Publication date
JPS63175439A (en) 1988-07-19

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