JPH06101715B2 - Multiplex / separation method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a multiplexing / demultiplexing method for multiplexing data and demultiplexing the multiplexed data.

[Background of the Invention]

The conventional multiplex / demultiplex method, as described on pages 67 to 69 of "Digital Circuit" (edited by The Institute of Electronics, Information and Communication Engineers, published by Corona Publishing Co., Ltd.), selects multiple inputs periodically and outputs one output. On the contrary, one input is periodically separated into a plurality of outputs.

However, the above-mentioned multiplexing / demultiplexing system does not have a function of changing or changing the bit order within one time slot of input data at the time of multiplexing and demultiplexing.
Therefore, if the bit order needs to be changed or changed, a circuit for changing or changing the bit order is provided before or after the multiplexing section, and the bit order is changed or changed before or after the separating section. It was necessary to provide a circuit to restore the above. Therefore, in the conventional multiplexing / demultiplexing system, when the bit order in one time slot of input data is changed or changed, the device becomes large and the cost becomes high.

[Object of the Invention]

The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a multiplexing / demultiplexing system having a function of changing the bit order within one time slot of input data and changing the bit data. I am trying.

[Outline of Invention]

The multiplexing / demultiplexing system of the present invention is a multiplexer for receiving a plurality of input data, each time slot of which is composed of a predetermined number of bits, through a plurality of input lines, and multiplexing and outputting the input data group. And a demultiplexing unit for receiving the output of the multiplexing unit via an input line and demultiplexing and outputting to a plurality of output lines. In particular, the multiplexing unit Means for performing order conversion of bit data in one time slot of a plurality of input data and changing bit data are provided, and the demultiplexing section is one time slot converted / changed by the multiplexing section in demultiplexing. It is characterized in that it is provided with means for converting / changing the bit data in the original bit data before conversion / change.

Example of Invention

Hereinafter, the present invention will be described in more detail with reference to the embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of a multiplexing unit of the multiplexing / demultiplexing system of the present invention. In the figure, IN00 to IN31 are input lines, 1 is a selector for selecting the input lines IN00 to IN31,
2, 3 are memories for temporarily holding data when multiplexing, 4 are counters for generating sequential address signals (for example, consecutive addresses from 0 to 255) to the memories 2 and 3, 5 is a counter 4 Conversion unit for converting the output of the above into a random address signal (for example, 0,189,256 ...), 6,7
Is a selector for switching the address signal supplied to the memories 2 and 3 in accordance with the instruction of the read / write signal, and 8 is an inverter.

In FIG. 1, the selector 1 sequentially switches the input lines IN00 to IN31 according to the output of the counter 4. Input line
As shown in FIG. 2, data IN00S-IN31S having 8 bits for one time slot is input to IN00-IN31. The selector 1 sequentially switches the input lines IN00 to IN31 during the output period of the head bit of the data IN00S to IN31S, outputs the head bit data D ₀₀₀ , D ₀₁₀ , ... D _310, and outputs the data IN00S to IN31S.
During the output period of the second bit, the input lines IN00 to IN31 are sequentially switched to output the second bit data D ₀₀₀ , D ₀₁₀ , ... D ₃₁₀ , and the like, the eighth bit data D ₀₀₁ , D _011. 、… D
Outputs ₃₁₁ . That is, the counter 4 for switching the selector 1 is set to count 32 at each bit input time of the data IN00S to IN31S. As a result, the selector 1 outputs a data string as shown in FIG.

When the read / write signal RW is instructed to write while the selector 1 is outputting the data string shown in FIG. 3A, the memory 3 is set to write and the selector 7
Outputs the output of the counter 4 to the memory 3 as an address signal. As a result, at each address of the memory 3, the data output from the selector 1 is stored in the addresses 0 to 255, as shown in FIG. A logical value “1” is stored in advance at the address 256 of the memory 3.

Next, when the read / write signal RW is switched to the read instruction, the memory 3 is set to read and the memory 2 is set to write by the inverter 8. And selector 7
Outputs the output of the conversion unit 5 as an address signal, and the selector 6 outputs the output of the counter 4 as an address signal. As a result, the third address is stored in the addresses 0 to 255 of the memory 2.
The data output from the selector 1 is stored as shown in FIG. Further, since the output of the conversion unit 5 is input to the memory 3 as an address signal, it outputs a data string as shown in FIG. That is, the conversion unit 5 converts the sequential addresses 0 to 255 output from the count 4, and, for example, random addresses 0,128,256, ... 256,1,129,
256 ... 256, ..., 31,159,256 ... 256 is output. As a result,
The memory 3 outputs a data string as shown in FIG. After that, each time the write instruction / read instruction of the read / write signal RW is switched, the memories 2 and 3 alternately repeat the above-mentioned read / write.

Focusing on the input data IN00S input circuit IN00 in FIG. 2, the data row fifth bit th data D ₀₀₁ is shown in FIG. 4 is output to the second, the second to fourth bit th data
D ₀₀₀ and the data D _{001 at} the 6th to 8th bits are ignored, and the 3rd to 8th data in the data string shown in FIG. 4 are output as "1". The other input lines IN01 to IN31 are code-converted and changed in the same manner.

As is apparent from the above description, according to this embodiment, 8 bits in one time slot of the input lines IN00 to IN31 (for example, in IN00, D ₀₀₀ , D ₀₀₀ , D ₀₀₀ , D ₀₀₀ , D ₀₀₁ , D ₀₀₁ , D ₀₀₁ ,
8 bits arranged in the order of D ₀₀₁ and D ₀₀₁ are code-converted (D ₀₀₀ , D ₀₀₁ , 1,1,1,1,1,1 in IN00) are output. That is, as described above, by arbitrarily setting the conversion unit 5, the read addresses of the memories 2 and 3 are converted at random, and the memories 2 and 3 are read alternately at random, so that 32 Input data IN00 of input lines IN00 to IN31
Not only can S-IN31S be multiplexed, but bit conversion and the contents of specific bits can also be changed.

FIG. 5 is a block diagram showing an embodiment of the demultiplexing unit of the multiplexing / demultiplexing system of the present invention. The same parts as those of the multiplexing unit in FIG. 1 are designated by the same reference numerals. In FIG. 5, for example, a data string as shown in FIG. 4 is input via the input line IN. Such a data string is stored in the memory according to the read / write instruction of the read / write signal RW.
It is written alternately in 2 and 3. At that time, the selectors 6 and 7 select the output of the counter 4 as the address signal,
Output to 3. Accordingly, the memories 2 and 3 store the respective bits of the data string as shown in FIG. 4 at sequential addresses. The data strings alternately written in the memories 2 and 3 are alternately read from the memories 2 and 3 in accordance with the read / write instruction of the read / write signal RW. As the address signal at this time, the selectors 6 and 7 select the output of the conversion unit 5. Therefore, the memories 2 and 3 are randomly read and the code order is changed. The data strings alternately output from the memories 2 and 3 according to the read / write signal RW are distributed by the decoder 9 to the output lines OUT00 to OUT31. The decoder 9 distributes the data output from the memories 2 and 3 to the output lines OUT00 to OUT31 according to the random address signal output from the conversion unit 5. Therefore, the first
Data separation and code conversion can be performed according to the same principle as that of the multiplexing unit shown in the figure.

Explaining using a specific example, when the data string shown in FIG. 4 is transmitted via the input line IN, it is stored in one of continuous addresses 0 to 255 of the memory 2 or 3. Memory 2
Or, when reading out 3, pay attention to the output line OUT00,
In order to output the same data as the data IN00S shown in FIG. 2, the converter 5 converts the output of the counter 4 and outputs it.

Incidentally, in the embodiment described above, writing to the memories 2 and 3 is performed by a sequential address signal,
Although the reading is performed by using a random address signal, the present invention is not limited to this, and writing may be performed by a random address signal and reading may be performed by a sequential address signal. Both writing and reading may be performed by random address signals.

Further, in the embodiments described above, the memories 2 and 3 are used for holding data, but individual ICs (for example, flip-flops, shift registers, etc.) may be used, or the memory may be used.
The entire circuit shown in the figure may be implemented as an LSI.

Further, in the above-described embodiment, the description has been made assuming that there are 32 input lines, 1 output line and 1 input line, and 32 output lines, but the present invention is not limited to this.
The number of input lines and output lines may be arbitrary.

〔The invention's effect〕

According to the present invention, since code conversion can be performed at the same time as data demultiplexing, there is an effect that an economical communication system can be provided without installing a special code conversion circuit in addition to the conventional demultiplexing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a multiplexer of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing input data input through the input line shown in the embodiment of FIG. 1, and FIG. a) is the first
FIG. 3 is an explanatory diagram showing a data string output from the selector in the embodiment shown in FIG. 3, and FIG. 3 (b) is an explanatory diagram showing the relationship between data and addresses stored in the memory in the embodiment shown in FIG. FIG. 4 is an explanatory diagram showing an example of the multiplexed output in the embodiment shown in FIG. 1, and FIG. 5 is a block diagram showing a demultiplexing unit of an embodiment of the present invention. 1,6,7 …… Selector, 9 …… Decoder 2,3 …… Memory 4 …… Counter 5 …… Converter 8 …… Inverter

Claims (1)

[Claims] 1. A multiplexing unit for receiving a plurality of input data whose time slot is composed of a predetermined number of bits via a plurality of input lines, multiplexing the input data group, and outputting the multiplexed data. In the demultiplexing / demultiplexing system, the demultiplexing unit receives the output of the unit via the input line and demultiplexes into a plurality of output lines and outputs the demultiplexed unit. Means for converting the order of the bit data in one time slot of the input data and changing the bit data are provided, and the demultiplexing section stores the data in the one time slot converted / changed by the multiplexing section at the time of demultiplexing. Multiplexing characterized by having means for converting / changing bit data to original bit data before conversion / change
Separation method.