JPH06103495B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention specifies a plurality of vector registers that can be read and written at arbitrary timings, receives data from the vector registers, performs an operation, and specifies an operation result by an instruction. The present invention relates to an information processing apparatus having a vector arithmetic unit for sequentially writing to the vector register and a data transfer path, and having a function of starting an arithmetic operation from an arbitrary vector element of a vector register designated by an instruction.

[Conventional technology]

Conventionally, in this type of information processing apparatus, when the operation is performed by the number of elements sequentially specified by the vector length register from the operation start element specified by the instruction, the source register of the preceding instruction (operated data storage register) Destination register of the instruction that follows (operation result storage register)
And the area where the preceding instruction reads the data required for the operation and the area where the subsequent instruction writes the operation result overlap, the subsequent instruction is processed in parallel with the preceding instruction, and the preceding instruction is required for the operation. Since the subsequent instruction may write the operation result to the area before reading the appropriate data and reverse the causal relation of the operation result, in order to guarantee the order of instruction execution, at least FIG. As shown, it is sufficient to guarantee that the writing of the operation result of the succeeding instruction does not precede the reading of the operation data of the preceding instruction, but as shown in FIG. 3B, the preceding instruction is completely completed. It was controlled to wait for and start the corresponding subsequent instruction.

[Problems to be solved by the invention]

In the above-described conventional information processing apparatus, the source register of the preceding instruction and the destination register of the succeeding instruction match, and the area in which the preceding instruction reads the data necessary for the operation and the area in which the succeeding instruction writes the operation result are When they overlap, the control is performed so that the corresponding subsequent instruction is started after waiting for the preceding instruction to be completely completed, which causes a disadvantage that the waiting time is wasted and the vector processing efficiency is significantly reduced.

[Means for solving problems]

The information processing apparatus of the present invention is a vector operation in which a plurality of vector registers read and written at arbitrary timings and data from the vector registers are operated and operated, and the operation results are sequentially written into the vector register designated by an instruction. And a data transfer path, and an information processing device having a function of starting an operation from an arbitrary vector element of a vector register designated by an instruction, wherein a vector register for reading out operated data of a preceding instruction and a subsequent When the vector register for writing the operation result of the instruction is the same, the write position acquisition means for acquiring the write element position to the vector register by the subsequent instruction, and the operation for acquiring the time required for the operation of the subsequent instruction The calculation from the time acquisition means and the write element position acquired by the write position acquisition means Subtraction means for subtracting the time acquired by the time acquisition means, read position acquisition means for acquiring the read start element position of the vector register by the preceding instruction, and read start element position acquired by the read position acquisition means The control unit includes a comparison unit that compares the subtraction result of the subtraction unit, and controls activation of the subsequent instruction according to the result of the comparison unit.

[Operation] Therefore, useless waiting at the time of activating a vector instruction is reduced, and the vector processing efficiency is improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of an information processing apparatus of the present invention, FIG. 2 is a block diagram of a part related to instruction activation in a control unit 4, and FIG. 3 (a) is a block diagram of this embodiment. It is a time chart figure which shows an effect.

The information processing apparatus according to the present embodiment receives a plurality of vector registers V0, V1, V2, ..., Vn that can be read and written at arbitrary timings, receives data from these vector registers V0 to Vn, performs an operation, and issues an operation result instruction. , 2d for sequentially writing to the vector register designated by 1 and 2, the data transfer path 1, and the control unit 4.

The control unit 4 determines the function unit time (FU) of the instruction from the instruction holding register 41 that holds the instruction that is about to be activated and the instruction information that is held in the instruction holding register 41.
T: Decoder 42 for decoding the time from reading the data to be operated to writing the first operation result in the register), and storing the operation result of the instruction among the instruction information held in the instruction holding register 41 Information n ₂ indicating the starting point and the decoder 42
Of the output fut ₂ of the subtracter 43, the register 44 for instructing the operand data read element number of the preceding instruction, and the operand data read element number is the output n ₂ -fut ₂ of the subtractor 43.
Comparator 45 for detecting that the instruction has been exceeded and whether or not the instruction held in the instruction holding register 41 can be activated from the information such as the usage status of the arithmetic units 2a to 2m in response to the detection signal from the comparator 45. The instruction activation control unit 46 is configured to determine and activate the instruction activation signal when activation is possible.

Next, the operation of this embodiment will be described.

As shown in FIG. (The vector registers V0 and V1 are sequentially calculated from the n1th element and stored in the vector register V2), (Vector register V3 and V4 are calculated and vector register
Sequentially store from the n2th element to V0), the read start element n1 for the vector register V0 of the preceding instruction is the read element number holding register
It is set to 44 and is counted up in synchronization with the progress of calculation. On the other hand, the subsequent instruction is set in the register 41,
The operation result storage start element n2 of the instruction and the operation result of the instruction
FUT = fut ₂ is decoded, subtracter 43 obtains n ₂ −fut ₂ ,
The comparator 45 compares the read element number of the operand data of the preceding instruction. Preceding instruction operand read element number <of n2-fut ₂ relationship said prior instruction at the time it was initiated, i.e. a state subsequent operation result preceding the data area to be written instruction is not yet read, thus Subsequent instructions will not be activated. Run start to subsequent instruction preceding execution of instructions proceeds becomes read element number> of n2-fut ₂ relationship operand data and the instruction start control unit 46 then is applied. Fut ₂ hours after this time n2 of vector register V0
For the element, the data reading of the preceding instruction and the writing of the operation result by the succeeding instruction are performed at the same time, and thereafter n2 + 1, n2 + 2, ...
The instructions are executed with no waste and the order of the instructions is preserved.

〔The invention's effect〕

As described above, in the present invention, when the vector register from which the preceding instruction reads the operated data and the vector register in which the succeeding instruction writes the operation result are the same, the reading of the operated data by the preceding instruction is not executed yet. By detecting that the operation result storage start point of the subsequent instruction has been passed and controlling the start of the instruction so that the operation result of the subsequent instruction is started at the time of detection, unnecessary waiting at the time of starting the vector instruction is reduced. Therefore, there is an effect that efficient vector processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of an information processing apparatus of the present invention, FIG. 2 is a block diagram of a part relating to instruction activation in a control unit 4, and FIG. It is a time chart shown in comparison with. V0.V1, ..., Vn ... Vector register, 2a, 2b, ..., 2m ... Vector operation unit, 3 ... Data transfer path, 4 ... Control unit, 41 ... Instruction holding register, 42 ... Decoder, 43 …… subtractor, 44 …… register, 45 …… comparator, 46 …… instruction activation control section.

Claims (1)

[Claims] 1. A plurality of vector registers that are read and written at arbitrary timings, a vector arithmetic unit that receives data from the vector registers, performs an arithmetic operation, and sequentially writes the arithmetic result to the vector register designated by an instruction, and data. In an information processing device having a transfer path and having a function of starting an operation from an arbitrary vector element of a vector register designated by an instruction, a vector register for reading out operated data of a preceding instruction and an operation result of a succeeding instruction are displayed. When the vector register to be written is the same, a write position acquisition means for acquiring a write element position to the vector register by the subsequent instruction, and an operation time acquisition means for acquiring a time required for the operation of the subsequent instruction, From the write element position acquired by the write position acquisition means, the calculation time acquisition means Subtraction means for subtracting the time acquired by the read instruction, read position acquisition means for acquiring the read start element position of the vector register by the preceding instruction, read start element position acquired by the read position acquisition means, and the subtraction means An information processing apparatus, comprising: a comparison unit that compares the subtraction result according to step 1 above, and a control unit that controls the activation of the subsequent instruction according to the result of the comparison unit.