JPH077386B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to control of a vector operation having a plurality of vector registers writable / readable at arbitrary timing, and particularly to an instruction specifying an operation start element by an instruction. Regarding operation start control.

(Prior Art) Conventionally, in an information processing apparatus having a plurality of vector registers that can be read / written at arbitrary timing, the start element designated by an instruction is sequentially designated by a vector length register. The number of elements to be calculated is calculated. In this case, if the storage register of the operation result of the preceding instruction is the operation source register of the subsequent instruction,
When the operation start element is the 0th element (0 origin: means the first element), the operation result of the first element of the preceding operation instruction is the same as the other operation as shown in FIG. Written to vector register. At the same time, the operation result is read out, and the subsequent instruction is activated so that it can be used for the subsequent instruction. However, when the operation start element is not the 0th element, as shown in FIG. 3 (b), when the operation result is completely written to the vector register by the preceding operation instruction, that is, when the preceding operation instruction is completed. The subsequent instruction is being activated.

In the above operation, it is guaranteed that the operation result of the preceding instruction is stored in the operation source element of the subsequent instruction before the operation is executed. The operation start element is specified by the instruction, and the indefinite value that differs depending on the instruction. Therefore, when the start element is other than the 0th element, it is necessary to wait for the completion of the preceding instruction.

(Problems to be Solved by the Invention) As can be easily understood from FIG. 3 (b), the above-described conventional information processing apparatus has a sequence of instruction execution when the operation start element is other than 0. In order to guarantee the above, the control is performed so as to start the operation after waiting for the preceding instruction that stores the operation result in the operation source register to be completely completed. Is stored, and even for the elements that can be operated by the subsequent instructions, it is waited until the execution of the preceding operation is completed.
There is a drawback that the improvement of performance is hindered.

An object of the present invention is to perform a vector operation for receiving a plurality of vector registers which can be read / written at arbitrary timings, data from the vector register and performing an operation and sequentially writing the operation result to a vector register designated by an instruction. And a data transfer path, the operation can be started from any vector element of the vector register specified by the instruction, and the operation result of the preceding instruction is written to the operation start element specified by the subsequent instruction. It is possible to eliminate the above-mentioned drawbacks by immediately starting the operation of the subsequent instruction when a write is detected, and to eliminate the need to wait until the execution of the preceding operation is completed. To provide.

(Means for Solving Problems) An information processing apparatus according to the present invention sequentially writes the vector data to a plurality of vector registers capable of reading / writing vector data at arbitrary timings and the plurality of vector registers. In the information processing device having a vector arithmetic unit for data processing and a data transfer path for starting an arithmetic operation from an arbitrary vector element stored in the vector register designated by the corresponding instruction, the arithmetic operation used by the preceding vector instruction Matching value is set by setting the added value of the machine cycle number and the number of vector elements of the device, counting down the added value for each machine cycle, and detecting the match between this value and the operation start element number specified by the subsequent instruction. A detection means is provided, and when the match detection means detects a match, the execution of the subsequent instruction is immediately started. As described above, a control unit for performing instruction activation control is provided.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In FIG. 1, 11, 12 ... 1n are a plurality of vector registers capable of reading / writing vector data at arbitrary timings, and 21 ... 2n are vectors stored in the vector registers 11, 12 ... 1n. An arithmetic unit for sequentially reading out data, executing an arithmetic operation, and storing it in the vector register 11, 12 ... 1n designated by the instruction,
Reference numeral 3 is a data transfer path for transferring vector data between the vector registers, and 4 is a control unit for controlling activation of an instruction for operating the above-mentioned components. In the control unit 4, 41 is an instruction register for temporarily storing an instruction, 42
Is a vector length register for specifying the vector length when executing a vector instruction, 43 is the instruction information held in the instruction register 41, and this instruction is necessary for processing one element of vector data. Machine cycle count (fut:
Function Unit Time) output instruction decoding unit, 44
Is an adder for adding fut and the vector length value (vl: Vector Length) read from the vector length register 42, and 46 is a one-to-one correspondence with the vector register, and writes vector data to the vector register. When the instruction to be executed is activated, the above addition result is set, then the countdown is continued for each machine cycle, and the counter for detecting the timing for resetting the write busy flag of the Vecule register, 45 is the vector length register The value of the vector length read from 42 (v
l) and a vector start element sy read from the instruction register 41, a subtracter 47 calculates a detection output when the value of the counter 46 is equal to or smaller than the output value of the subtractor 45. It is a coincidence detection circuit for sending.

The coincidence detecting means corresponds to a portion including the adder 44, the subtractor 45, the subtraction counter 46, and the coincidence detecting circuit 47.

Next, the operation of the present invention will be described with reference to the example of FIG.

Now, it is assumed that the calculation of V2 ← V0 + V1, V3 ← V2 (sy) is executed. That is, the vector data stored in V0 and V1 are added to the vector length register 42 from the element 0 by the number of elements indicated by the vector length register 42, and stored in V2. The operation of transferring to V3 by the number of elements indicated by the above shall be executed.

FIG. 2 is a time chart for executing the example of FIG. At time t ₀ , vl + output from the adder 44
The value of fut is set in the subtraction counter 46, and at the same time the preceding instruction V
2 ← Activate V0 + V1. After that, while counting down the value of the counter 46 for each machine cycle, V2 ←
The operation of V0 + V1 is executed one element at a time starting from element 0. At time t ₁ , that is, after the (fut + sy) machine cycles from the start of the calculation, the value of the subtraction counter 46 is (fut + vl) − (fut
+ Sy) = vl-sy, and the output of the subtractor 45 is equalized, and the coincidence detection circuit 47 detects the coincidence. This match signal activates the subsequent transfer instruction V3 ← V2 (sy).

As a result, at the timing when the result of the element sy of the preceding operation instruction is written in the target register V2, the element can be read and the transfer to the transfer destination register V3 can be started.

(Effect of the invention) As described above, according to the present invention, when the operation of the execution result of the preceding operation instruction is started from the operation start position designated by the subsequent instruction, the order of the instructions is guaranteed, and therefore the operation start element is preceded by the operation start element. By controlling so that the subsequent instruction can be started at the time when the result of the operation is written, it is possible to reduce wasteful waiting at the time of activating an instruction and improve the vector processing efficiency. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. FIG. 3 is a time chart for explaining the operation of transferring the operation result of the preceding instruction according to the prior art starting from element 0 or sy. 11,12,1n …… Vector register 21,2n …… Calculator 3 …… Vector data transfer path 4 …… Vector instruction control unit 41 …… Instruction register 42 …… Vector length register 43 …… Instruction decoder 44 …… Addition Unit 45 …… Subtractor 46 …… Subtraction counter 47 …… Match detection circuit

Claims (1)

[Claims] 1. A plurality of vector registers capable of reading / writing vector data at an arbitrary timing, a vector arithmetic unit for sequentially writing the vector data in the plurality of vector registers, and designated by a corresponding instruction. In an information processing device equipped with a data transfer path for starting an operation from an arbitrary vector element stored in a vector register, the added value of the machine cycle number of the arithmetic unit used by the preceding vector instruction and the number of vector elements Is set, count-down of the added value is performed for each machine cycle, and a match detection unit for detecting a match between this value and the operation start element number designated by the subsequent instruction is provided, and the match detection unit detects a match. When it does, it is equipped with a control unit for performing instruction activation control so as to immediately start the execution of the subsequent instruction. A characteristic information processing device.