JPH0610789B2 - Anomaly detection device using microcomputer - Google Patents

Description

The present invention erroneously determines that an abnormality has occurred due to a malfunction such as a so-called garbled RAM value in which the contents stored in a random access memory change even though no abnormality has occurred. It is an abnormality detection device that uses a microcomputer to prevent the detection by the above. When an abnormal state continues for a predetermined first time W1 (for example, 1.0 second), it is determined that an abnormality has occurred. Whether or not the output of the abnormal state detecting means for detecting whether or not each of the plurality of items is abnormal is continued for the second time W2 (for example, 0.8 seconds, W2 <W1) predetermined by the first abnormal continuation detecting means. After the abnormal state continues for the second time after being detected in the item, the third abnormal time W3 further predetermined by the second abnormal continuation detecting means.
It detects if it lasted (eg 0.2 seconds, W1 = W2 + W3) and thus a total of two first and second
When an abnormal condition is detected by the abnormal continuation detecting means, it is determined that an abnormality has occurred, information indicating that the abnormality has occurred is stored in the store cell corresponding to each item of the register, and the store cell of this register is stored. Whether or not the contents of the store are correct is judged by the judgment means. In this way, it is possible to prevent the malfunction of the first abnormality continuation detection unit from erroneously detecting that an abnormality has occurred, even though no abnormality has occurred in each item.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting an abnormal state of a device for controlling an internal combustion engine using a microcomputer.

2. Description of the Related Art With the use of microcomputers in the control of internal combustion engines and the like, various additional functions have been added by utilizing their functions, and one of them is a self-diagnosis function. Taking an internal combustion engine as an example, the operation of sensors and actuators is monitored, and if an abnormality is detected, a warning is given to the driver, or the abnormality is stored in advance, and if a predetermined operation is performed in a maintenance shop, the The content of the abnormality is displayed. This function enables quick detection of abnormalities and identification of abnormal parts, improving maintainability and reliability.

However, on the other hand, if some malfunction (for example, a RAM value is garbled due to noise or the like) is mistakenly detected as an abnormality, the driver will feel unnecessary anxiety, and expensive parts that are not abnormal will be replaced. .

Some prior art will be described with reference to FIGS. In this prior art, when controlling an internal combustion engine, random access memories RX1 to RX1 for storing abnormal items are used.
RX3 is provided, and these memories RX1 to RX are further provided.
Another random access memory RS for monitoring 3
A UM is provided and configured to detect whether or not so-called RAM garbled in which the stored contents of the memories RX1 to RX3 change due to noise or the like has occurred.

Each 8-bit store cell of the memories RX1 to RX3 is used to detect an abnormal state of up to 24 items. Each of the memories RX1 to RX3 has 0th to 7th bit store cells. For example, as shown by hatching in FIG. 12, when it is detected that the item corresponding to the sixth bit of the memory RX2, for example, the inspection item of the cooling water temperature sensor is abnormal, the memory RX2 of the memory RX2 is detected. Sixth
At the same time that the bit is set to logic "1", and if the sixth bit before being set is logic 0, the memory R
Add 64 (= 2 ⁶ ) to SUM. As a result, the value of the memory RSUM becomes the total value of the memories RX1 to RX3.

Therefore, the memories RX1 to RX3 and the memory RSUM are regularly checked, and when the predetermined relationship is not maintained, the memories RX1 to RX3 or RSUM are erroneously rewritten for some reason, and thus the RAM value is garbled. I understand. At this time, the stored contents of the memories RX1 to RX3 and RSUM can be cleared and erroneous information can be erased to prevent a problem.

Such operation will be described with reference to FIG. The operation shown in FIG. 13 has a fixed period, for example, 50 ms.
It is executed every ec. Upon judging the abnormality of the 6th bit of the memory RX2, the process moves from step n1 to step n2,
When the abnormal condition of the item corresponding to the sixth bit of the memory RX2 is not satisfied, that is, when the condition is normal, the content of the counter is set to zero in step n8. If the abnormal condition is satisfied, the content of the counter is incremented by 1 in step n3.

In step n4, it is detected whether or not the content of the counter has continued for 1 second or more. If the abnormal state continues for 1 second or more, it is determined in step n5 whether the 6th bit of the memory RX2 is logic "1". If it is a logic "0", it is assumed that the logic "1" is rewritten in step n6, that is, it has changed from normal to abnormal, and in step n7, 2 ⁶ is added to the content of the memory RSUM.

Referring to FIG. 14, in determining whether the RAM value is garbled, the process proceeds from step 1 to step 2, and the value obtained by adding the binary information to each store cell of the memories RX1 to RX3 is equal to the content of the memory RSUM. If it is not equal, it is determined that the RAM value is garbled, and all the memory RX is determined in steps to 6.
1 to RX3, reset the stored contents of RSUM to zero.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a prior art, a memory RX for storing an abnormal item is provided.
1 to RX3 and its monitoring memory RSUM have been taken as measures against garbled RAM values, but no measures have been taken against, for example, a configuration for determining abnormality occurrence. In the above-mentioned prior art, in step n4 of FIG. 13, if a certain state continues for 1 second or more, it is determined that an abnormality has occurred, but if the counter is rewritten to a large value for some reason, an abnormality occurs. Even though it is not, it is determined that an abnormality has occurred.

In order to solve this problem, it is conceivable to provide a random access memory for monitoring each of the counters provided for each store cell of the memories RX1 to RX3, but this is done. The storage capacity increases and the processing becomes complicated.

An object of the present invention is to provide an abnormality detection device using a microcomputer that accurately detects an abnormal state, suppresses an increase in storage capacity, and is simple in processing.

Means for Solving the Problems The present invention should detect whether or not there is an abnormality in an abnormality detection device that uses a microcomputer that determines that an abnormality has occurred when an abnormal state is continuously detected for a predetermined first time W1. For each of a plurality of multiple items, a unit for detecting an abnormal state for each item, and a unit provided for each item for detecting whether or not the output of the abnormal state detection unit has continued for a predetermined second time W2 1 Abnormality continuation detecting means and in response to the outputs of the first abnormal continuation detecting means, the abnormal state continues by the first abnormal continuation detecting means for a second time W2, and then continues for a predetermined third time W3. Whether or not it is provided in common for each item, the second
The sum of the time and the third time is set to the first time W1, the second abnormal continuation detecting means, the memory having the store cell corresponding to each item, and the output of the second abnormal continuation detecting means. In response to an abnormal condition
And a means for storing information indicating the abnormal state in the store cell corresponding to the item in which the abnormal state has occurred, and determining whether or not the stored content of the store cell of the memory is correct when continuing for a third time. An abnormality detection device using a microcomputer, which includes:

Operation According to the present invention, an abnormal state detecting means is provided for each of a plurality of items for which whether or not an abnormality is detected, and the register has a store cell corresponding to each item. The first abnormal continuation detecting means is responsive to the output of the abnormal state detecting means, and the abnormal state detected thereby is predetermined for the second time W2.
The first abnormal continuation detecting means is provided for each item. The second abnormality continuation detecting means further determines a predetermined third time W after the first abnormality continuation detecting means for each item continues for the second time W2 of the abnormal state.
3 (W1 = W2 + W3) is detected.
The second abnormality continuation detecting means is provided in common for each item, thereby simplifying the configuration.

On the basis of the output of the second abnormality continuation detecting means, the abnormal state is over the second and third time periods, that is, during the first time period,
When it continues, it is determined that an abnormal state has occurred for the item, and information indicating the abnormal state is stored in the corresponding store cell of the memory. Whether or not the stored content of the store cell of the register is correct is detected by the judging means, for example, periodically.

Embodiment FIG. 1 is an overall block diagram of an embodiment of the present invention. The operating state of the internal combustion engine is determined by a plurality of sensors S1 to S24.
Detected by. The outputs of these sensors S1 to S24 are given to the processing circuit 3 realized by the microcomputer via the analog / digital converter 1 and via the input interface 2. The processing circuit 3 is provided with a random access memory 4 and is constantly energized by a power source 5 to hold the stored contents of the random access memory 4. In the processing circuit 3, when it is determined that an abnormality has occurred in the item detected by the sensors S1 to S24, the abnormality occurrence display 6 displays the fact.

FIG. 2 is a simplified block diagram for explaining the configuration of the processing circuit 3 shown in FIG. Sensors S1 to S
The output of 24 is individually given to the abnormal state detecting means E1 to E24, and it is detected for each of these items whether or not there is an abnormality. The outputs of the abnormal state detecting means E1 to E24 are detected by the counters C1 to C24 for the duration of time. The output of each of the counters C1 to C24 is selectively switched by the changeover switch 7 and is given to the other counter A1, and the output of the counter A1 and the output of the changeover switch 7 are given to the AND gate G1. The process is performed assuming that an abnormal state has occurred. The counters C1 to C24 are generally denoted by the reference symbol C.

In this embodiment, when the state detected by the sensors S1 to S24 is determined to be an abnormal state by the abnormal state detection means E1 to E24, the abnormal state is a predetermined first time W1 (for example, 1.0 sec). ), It is judged that an abnormality has occurred. The counter C detects whether or not the abnormal state continues for a predetermined second time W2 (for example, 0.8 sec), and these counters C1 to C1.
C24 is provided for each of the sensors S1 to S24. The counter A1 is provided in common for each of these items, and after the abnormal state is continued by the counter C for the second time W2, the counter A1 is further set for a predetermined third time W3 (for example, 0.2 sec).
c, W1 = W2 + W3) is detected. In this way, when the abnormal state continues for the first time W1 or more, a signal indicating that the abnormal state has occurred is derived from the AND gate G1, and a predetermined processing operation in the abnormal state, for example, display is performed. The schematic configuration shown in FIG. 2 will be described in more detail below.

FIG. 3 is a block diagram showing components included in the processing circuit 3. Total of 3 random access memories RX
1 to RX3 each have a 0th to 7th bit store cell, and each store cell is a sensor S1 to S2.
It corresponds to each of the four detection items individually. Furthermore, a random access memory RSUM is provided, which is for monitoring the memories RX1 to RX3, and this memory RSUM
Also has a total of 8 bits of store cells and has memory RX1
~ The binary numbers represented by RX3 are added and stored.

The random access memory RX4 has a store cell that individually corresponds to an item that is determined to have occurred abnormally for the first time W1 or more for the first time W1 or more out of a total of 24 items to be inspected. It may have 24 store cells or less store cells, for example, 8 in this embodiment.
Such items to be continuously detected may be, for example, the cooling water temperature and the intake air temperature of the internal combustion engine.

The processing circuit 3 also includes a counter C, a register A, a register B, and a counter A1. The memory RX4 is a random access memory for operating the counter A1,
The initial value is a logic "0" for all the store cells, and is used to determine whether or not the abnormality is detected the last time in the processing operation. The counter A1 has a predetermined time, for example, 4 msec, set by a routine provided separately.
It is a counter that increments from zero to a maximum FF every time. In the present embodiment, the above-described memory RX4 will be described below assuming that eight store cells are provided corresponding to eight items to be detected, for example.

With respect to the item that is determined to be abnormal in the memory RX4, it is determined that the abnormality has occurred due to the continuation of the abnormal state for the first time W1 or more, and therefore the counter C and the counter A1 are used. Therefore, even if at least one of the counter C and A1 has a garbled RAM value due to noise or the like, it is immediately determined that an abnormality has occurred, and the memory RX
It is possible to prevent the abnormality occurrence information from being stored in the corresponding store cell of No. 4. Of these counters C and A1, one counter A1 is common for a plurality of items that are determined to be in an abnormal state when the second time W2 or more continues, thereby enabling a significant reduction in store capacity.

FIG. 4 is a waveform diagram for explaining the operation of each component shown in FIG. 3, and FIG. 5 is a flow chart for explaining the operation for judging that the abnormal state has occurred. . With reference to these drawings, for example, regarding the detection item corresponding to the 6th bit of the memory RX2,
The operation when it is determined that an abnormality has occurred due to the continuation of the abnormal state for the time W1 or more will be described.

The operation shown in FIG. 5 is performed, for example, every 50 msec. When the output of the sensor S15 corresponding to the 6th bit of the memory RX2 is not judged to be in the abnormal state by the abnormality detecting means E15, that is, when the output is normal, the counter is counted in step g12. C is made zero as shown in FIG. 4 (1). When the abnormality detecting means E15 detects an abnormality, the process proceeds to step g3, and the content of the counter C is incremented by 1.

At step g4, the memory R is used for the arithmetic processing described later.
2 ⁰ (two logic “1”) is stored in the 0th bit of the register B corresponding to the 6th bit of X2. In step g5, when the stored content of the counter C is C, (C-
0.8 sec) is calculated. At step g6, the contents of the counter A1 described later are checked. Step g6a
Then, it is determined whether the content of the counter C is less than 0.8 sec, and if it is less than 0.8 sec, then step g7
Move on to. In step g7, it is determined whether the stored content of the counter A1 is 0.2 sec or more, and if so, it is determined that an abnormality has occurred, and the process proceeds to step g8. At step g8, the memory RX corresponding to this sensor S15
It is determined whether or not the logic of the 2nd 6th bit store cell is "1". If not, it is stored in the logic "1" in step g9.

At step g10, in order to determine whether the stored contents of the store cells of the memories RX1 to RX3 are correct, the stored contents of the memory RSUM are updated by adding the value ²⁶ corresponding to the above-mentioned sixth bit. The sixth of this memory RX2
The operation of storing a logical "1" in a bit is shown in Fig. 4 (4).
As shown in.

FIG. 6 is a flow chart for explaining the operation for checking whether the counter A1 shown in FIG. 4 (2) is operating normally. When the stored content of the counter C is set to C, it is determined whether (C-0.8) is zero or more, and otherwise, it is determined that the inspection item is normal. Judgment, and it moves to step r3. The register B used here is used only for an arithmetic operation, and the inversion of each cell of the register B is as shown in FIG. Memory RX4
AND of the inversion of the register B is obtained in step r3, and the logical operation result of AND (logic "0" in this embodiment) is stored in the store cell of the 0th bit memory RX4.

Therefore, the operation of executing steps r2 to r3 is executed in the normal state and within less than 0.8 seconds after the abnormality occurs. From step r2 to step r8 described next, the operation of resetting the counter A1 is shown when the 0th bit of the memory RX4 becomes the logic "1", that is, when the abnormal state continues for 0.8 seconds. The stored contents of the 0th bit of this memory RX4 are
This is shown in FIG. 4 (3).

If the content stored in the counter C continues to be abnormal for 0.8 seconds, the process moves from step r2 to step r5. At step r5, the contents stored in the memory RX4 are transferred to the register A. When step r5 is executed for the first time, the 0th bit shown in FIG. 8 of the register A has a logic "0". In step r6, the AND operation of the registers A and B is logically operated. As shown in FIG. 8, among the operation results of AND of these registers A and B, the 0th
If bit X is logical "0", the result is logical "0"
If X is a logical "1", the result is a logical "1".
It is determined that If the content X of the 0th bit of the logical operation result is logical "0" by the AND logical operation result of the registers A and B, the counter A1 is cleared to zero in step r7, and then the counter A1
Is incremented and the clocking operation is performed. After the steps r2 to r8 are first executed, the 0th bit of the AND logic operation result of the registers A and B is the logic "1".
That is, it was judged that the previous time was also abnormal,
Move to step r8.

At step r8, as shown in FIG.
The OR logic operation of each store cell of X4 and the register B is performed, and the result is stored in the memory RX4. In FIG. 9, X means a logic "0" or a logic "1". The 0th bit of the memory RX4, in which the OR logical operation result is stored, is set to logic "1", whereby it is determined that the water temperature of the internal combustion engine detected by the sensor S15 corresponding thereto has become abnormal, and an abnormality occurs. Is detected.

In summary, the abnormal state of the counter C is the second time W.
After 0.8 seconds, which is 2, the counter A1 first resets the counter A1 to zero in order to perform the timekeeping operation with the counter A1, and thereafter, from step r6, without moving to step r7. Moving to step r8, the counter A1 is incremented and clocked by another routine as described above. When the counter A1 has passed the third time of 0.2 seconds or more, it is determined that an abnormality has occurred in step g7 of FIG. 5 as described above, and the next step g8 is executed.

In the above-described embodiment, the binary numerical values of the memories RX1 to RX3 are added to detect the garbled RAM value, and it is determined whether or not the result matches the content of the memory RSUM. However, as another embodiment of the present invention, the RAM garbled value may be checked by the configuration shown in FIGS. 10 and 11. First
As shown in FIG. 0, in addition to the memories RX1 to RX3 described above, memories RX11 to RX31 are further provided. The same contents as the memory RX1 are stored in the corresponding memory RX11, and the contents stored in RX2 and RX3 are the same as R in the same manner.
It is also stored in X21 and RX31.

Step (u1) to step (u2) in FIG. 11 (1)
After it is determined that an abnormality has occurred, in step u3, for example, the memory RX2 corresponding to the abnormality has been detected.
The store cell of the 6th bit of is set to logic "1", and in step u4, another memory RX corresponding to the memory RX2 is stored.
The sixth bit of 21 is set to logic "1".

Step (v1) to step (v2) in FIG. 11 (2)
Then, in order to detect the garbled RAM value, the memory RX1
It is determined whether or not the stored contents of the memory RX11 and the corresponding memory RX11 match. If they match, then the process moves to step v3, and it is determined whether the stored contents of the memory RX2 and the corresponding memory RX21 match. If they match, the process moves to step v4, and it is determined whether the stored contents of the memories RX3 and RX31 match. Any one of steps v2, v3, v4
If the two values do not match, it is determined that the RAM value is garbled, and the stored contents of the memories RX1 to RX3 and RX11 to RX31 are reset to zero in steps v5 to v10. In this way, the abnormality occurrence is detected again.

As described above, according to the present invention, when an abnormality is detected, the first abnormality continuation detecting means is provided for each item, and in response to the output of the first abnormality continuation detecting means, the abnormal state is further detected. Since the second abnormality continuation detecting means for detecting whether or not has continued is provided in common for each item, the abnormal state can be accurately detected and the configuration can be simplified. The processing can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a simplified diagram of the configuration of an embodiment of the present invention, and is a block diagram for easy understanding, and FIG. 3 is a processing circuit 3. FIG. 4 is a block diagram showing the components provided, FIG. 4 is a waveform diagram for explaining the operation of these components, FIG. 5 is a flow chart for explaining the operation for detecting the abnormality occurrence, and FIG. FIG. 7 is a flow chart for explaining the operation for checking the counter A1, FIG. 7 is a block diagram for explaining step r3 in FIG. 6, and FIG. 8 is operation for steps r5 and r6 in FIG. FIG. 9 is a block diagram for explaining the operation of FIG. 6, FIG. 9 is a block diagram for explaining the operation of step r8 in FIG. 6, and FIG. 10 is a simplified block diagram of another embodiment for detecting RAM garbled. , First
FIG. 1 is a flow chart for explaining the operation of the embodiment shown in FIG. 10 for detecting garbled RAM values,
2 is a simplified block diagram of the prior art, and FIGS. 13 and 14 are flowcharts for explaining the operation of the prior art shown in FIG. 1 ... Analog / digital converter, 2 ... input interface, 3 ... processing circuit, 4 ... memory, S1 to S24
...... Sensors, E1 to E24 ...... Abnormal state detection means, C,
C1 to C24 ... Counter, A1 ... Counter, A, B
...... Register, RX1 to RX4 ...... Memory, RSUM ...
…memory

Claims (1)

[Claims] 1. An abnormality detecting device using a microcomputer that determines that an abnormality has occurred when an abnormal state is continuously detected for a predetermined first time W1 for each of a plurality of items for which whether or not abnormality is to be detected. A means for detecting an abnormal state for each item, and a first abnormal continuation detecting means provided for each item for detecting whether or not the output of the abnormal state detection means has continued for a predetermined second time W2 In response to the output of the first abnormal continuation detecting means, the first abnormal continuation detecting means detects whether or not the abnormal state continues for a second time W2 and then continues for a predetermined third time W3. It is provided in common for each item, and the second
The sum of the time and the third time is set to the first time W1, the second abnormal continuation detecting means, the memory having the store cell corresponding to each item, and the output of the second abnormal continuation detecting means. In response to an abnormal condition
And a means for storing the information indicating the abnormal state in the store cell corresponding to the item in which the abnormal state has occurred, and determining whether the stored content of the store cell of the memory is correct, when continuing for the third time. An abnormality detection device using a microcomputer, which comprises: