JPH0611078B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0611078B2 JPH0611078B2 JP61221093A JP22109386A JPH0611078B2 JP H0611078 B2 JPH0611078 B2 JP H0611078B2 JP 61221093 A JP61221093 A JP 61221093A JP 22109386 A JP22109386 A JP 22109386A JP H0611078 B2 JPH0611078 B2 JP H0611078B2
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- film
- polyimide
- polyimide film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 11
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 12
- 238000007747 plating Methods 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000004132 cross linking Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に配線加工技
術に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring processing technique.
従来、この種の配線加工技術は、第３図(a)に示すよう
に電極２，３を有する半導体基板１上に絶縁膜４を形成
し、空間配線を施す電極２上の絶縁膜を除去し、次に第
３図(b)に示すようにポリイミド膜６でパターン形成す
る。次に第３図(c)に示すようにポリイミド膜６上に金
属膜７を形成しその後、第３図(d)に示すようにフォト
レジスト８でパターン形成後金属膜７を給電メタルとし
て電界めっきでAuめっき層９を形成し、次に第３図(e)
に示すようにAuめっき層９をマスクとして金属膜７を除
去し、最後に第３図(f)に示すようにＯ2プラズマによる
ドライエッチ又はヒドラジン系エッチャントでポリイミ
ド膜６で除去するようになっていた。Conventionally, this type of wiring processing technique is to form an insulating film 4 on a semiconductor substrate 1 having electrodes 2 and 3 as shown in FIG. Then, as shown in FIG. 3B, the polyimide film 6 is patterned. Next, as shown in FIG. 3 (c), a metal film 7 is formed on the polyimide film 6, and then, as shown in FIG. 3 (d), after patterning with a photoresist 8, the metal film 7 is used as a feeding metal to generate an electric field. The Au plating layer 9 is formed by plating, and then FIG. 3 (e)
The metal film 7 is removed by using the Au plating layer 9 as a mask as shown in FIG. 3, and finally, the polyimide film 6 is removed by dry etching using O 2 plasma or a hydrazine-based etchant as shown in FIG. 3 (f). Was there.
上述した従来の空間配線技術は完全にキュアしたポリイ
ミドを最後にＯ2プラズマ又はヒドラジン系エッチャン
トで除去するようになっているので、ポリイミドの除去
に長時間を要したり、配線幅が広い場合は完全にポリイ
ミドが除去できず、配線容量を低減できないという欠点
がある。In the conventional space wiring technique described above, the completely cured polyimide is finally removed by O 2 plasma or hydrazine-based etchant, so that it takes a long time to remove the polyimide or the wiring width is wide. There is a drawback that the polyimide cannot be completely removed and the wiring capacitance cannot be reduced.
上述した従来の空間配線技術に対し、本発明は架橋土台
として用いるポリイミド膜にフォトレジスト層が含まれ
ることにより架橋土台を除去する際薄いポリイミド膜を
除去すればヒドラジン系エッチャントにフォトレジスト
が融解することにより短時間で架橋土台を除去でき、ま
た、配線幅の広い空間配線が形成でき、配線容量の小さ
い高速半導体装置ができるという独創的内容を有する。In contrast to the conventional space wiring technology described above, the present invention includes a photoresist layer in the polyimide film used as the cross-linking base, so that the photoresist is melted in the hydrazine-based etchant if the thin polyimide film is removed when removing the cross-linking base. Thus, the bridge base can be removed in a short time, a space wiring having a wide wiring width can be formed, and a high-speed semiconductor device with a small wiring capacity can be obtained.
本発明の空間配線技術は、電極を形成した半導体基板上
に絶縁膜を形成し、空間配線を施す電極上の絶縁膜を除
去する工程と、空間配線を施す電極間の一部を覆うよう
なフォトレジストパターンを形成する工程と、フォトレ
ジストパターンを完全に覆うようなポリイミドパターン
を形成する工程とポリイミド膜上に金属膜を形成する工
程と、フォトレジストでパターン形成する工程と、金属
膜を給電メタルとしてAuめっきする工程と、Auめっき層
パターン状に金属膜を除去する工程とポリイミド膜及び
フォトレジストを除去する工程を有している。The space wiring technique of the present invention includes a step of forming an insulating film on a semiconductor substrate on which an electrode is formed, removing the insulating film on the electrode for performing the space wiring, and covering a part between the electrodes for performing the space wiring. Forming a photoresist pattern, forming a polyimide pattern that completely covers the photoresist pattern, forming a metal film on the polyimide film, forming a pattern with the photoresist, and feeding the metal film. It has a step of Au plating as a metal, a step of removing the metal film in a pattern of the Au plating layer, and a step of removing the polyimide film and the photoresist.
次に本発明について図面を参照して説明する。第１図は
本発明の一実施例の縦断面図である。１は半導体基板、
２，３は電極、４は絶縁膜、５，８はフォトレジスト、
６はポリイミド膜、７は金属膜、９はAuめっき層であ
る。Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view of an embodiment of the present invention. 1 is a semiconductor substrate,
2, 3 are electrodes, 4 are insulating films, 5 and 8 are photoresists,
6 is a polyimide film, 7 is a metal film, and 9 is an Au plating layer.
第１図(f)は本発明により得られる空間配線で、これは
同図(a)乃至同図(e)のようにして形成される。すなわち
まず第１図(a)に示すように電極２及び３を有する半導
体基板１上に絶縁膜４を形成し、空間配線で接続される
電極２上の絶縁膜を除去し、電極３上にフォトレジスト
でパターン形成する。次に第１図(b)に示すようにポリ
イミド膜６でパターン形成する。次に第１図(c)に示す
ように金属膜７（たとえばTi・Au）を形成する。次に第
１図(d)に示すようにフォトレジスト８でパターン形成
後、金属膜７をAuめっきの給電メタルとしてAuめっき層
９を約３μｍ形成する。次に第１図(e)に示すようにAu
めっき層９をマスクとして、金属膜７を除去する。最後
にＯ2プラズマを用いたドライエッチング及びヒドラジ
ン系エッチャントを用いたウェットエッチを用いて、ポ
リイミド膜６、フォトレジスト８を除去し第１図(f)の
構造を得る。FIG. 1 (f) shows a space wiring obtained by the present invention, which is formed as shown in FIGS. 1 (a) to (e). That is, first, as shown in FIG. 1A, the insulating film 4 is formed on the semiconductor substrate 1 having the electrodes 2 and 3, and the insulating film on the electrode 2 connected by the space wiring is removed to form the insulating film on the electrode 3. Pattern with photoresist. Next, as shown in FIG. 1 (b), the polyimide film 6 is patterned. Next, as shown in FIG. 1 (c), a metal film 7 (for example, Ti.Au) is formed. Next, as shown in FIG. 1D, after patterning with a photoresist 8, an Au plating layer 9 is formed to a thickness of about 3 μm using the metal film 7 as a feeding metal for Au plating. Next, as shown in Fig. 1 (e), Au
The metal film 7 is removed using the plating layer 9 as a mask. Finally, the polyimide film 6 and the photoresist 8 are removed by dry etching using O 2 plasma and wet etching using a hydrazine-based etchant to obtain the structure shown in FIG. 1 (f).
第２図は本発明の実施例２の縦断面図である。１は半導
体基板、５，１１はフォトレジスト、６はポリイミド
膜、１０は絶縁膜、１２は金属膜である。FIG. 2 is a vertical sectional view of a second embodiment of the present invention. Reference numeral 1 is a semiconductor substrate, 5 and 11 are photoresists, 6 is a polyimide film, 10 is an insulating film, and 12 is a metal film.
第２図(d)は半導体基板１上に金属膜１２をパターン加
工したもので、これは同図(a)乃至同図(c)のようにして
形成される。すなわち、まず第２図(a)に示すように半
導体基板１上にフォトレジスト５でパターン加工した
後、ポリイミド膜６を形成し、ポリイミド膜６上に絶縁
膜１０を形成し、さらにフォトレジスト１１でパターン
加工する。次に第２図(b)に示すようにフォトレジスト
１１のパターン状に絶縁膜１０をエッチングし、次に絶
縁膜１０をマスクとしポリイミド膜６をエッチングす
る。次に第２図(c)に示すように金属膜１２を形成す
る。最後にＯ2プラズマによるドライエッチング及びヒ
ドラジン系エッチャントによるウェットエンチングでポ
リイミド膜６及びフォトレジスト５を除去し、第２図
(d)の構造を得る。この実施例では金属膜１２を形成す
る場合表面がポリイミド膜６及び絶縁膜１０で覆われて
いるため耐熱性を有し、ポリイミド膜６中にフォトレジ
スト層５が含まれることからヒドラジン系エッチャント
によをウェットエッチングで容易に除去できる利点があ
る。FIG. 2 (d) shows the metal film 12 patterned on the semiconductor substrate 1, which is formed as shown in FIGS. That is, first, as shown in FIG. 2A, after patterning a photoresist 5 on the semiconductor substrate 1, a polyimide film 6 is formed, an insulating film 10 is formed on the polyimide film 6, and then a photoresist 11 is formed. Pattern processing with. Next, as shown in FIG. 2B, the insulating film 10 is etched in the pattern of the photoresist 11, and then the polyimide film 6 is etched using the insulating film 10 as a mask. Next, as shown in FIG. 2 (c), a metal film 12 is formed. Finally, the polyimide film 6 and the photoresist 5 are removed by dry etching with O 2 plasma and wet etching with a hydrazine-based etchant.
Obtain the structure of (d). In this embodiment, when the metal film 12 is formed, the surface is covered with the polyimide film 6 and the insulating film 10, so that it has heat resistance, and since the polyimide film 6 contains the photoresist layer 5, it becomes a hydrazine-based etchant. It has an advantage that it can be easily removed by wet etching.
以上説明したように本発明は、フォトレジストパターン
を完全に含んだポリイミド膜上に金属膜を形成した後、
ポリイミド膜及びフォトレジストを除去することによ
り、金属膜形成時には耐熱性を有し、ポリイミド及びフ
ォトレジスト除去時には短時間で容易に除去でき配線加
工できる効果がある。As described above, the present invention, after forming a metal film on the polyimide film completely containing the photoresist pattern,
By removing the polyimide film and the photoresist, it has heat resistance when the metal film is formed, and when the polyimide and the photoresist are removed, the polyimide film and the photoresist can be easily removed in a short time and wiring can be processed.
第１図は本発明の実施例１の縦断面図、第２図は本発明
の実施例２の縦断面図、第３図は従来の空間配線の工程
断面図である。 １……半導体基板、２，３……電極、４……絶縁膜、５
……フォトレジスト、６……ポリイミド縁、７……金属
膜、８……フォトレジスト、９……Auめっき層、１０…
…絶縁膜、１１……フォトレジスト、１２……金属膜。1 is a vertical sectional view of a first embodiment of the present invention, FIG. 2 is a vertical sectional view of a second embodiment of the present invention, and FIG. 3 is a process sectional view of a conventional space wiring. 1 ... Semiconductor substrate, 2, 3 ... Electrode, 4 ... Insulating film, 5
…… Photoresist, 6 …… Polyimide rim, 7 …… Metal film, 8 …… Photoresist, 9 …… Au plating layer, 10….
... Insulating film, 11 ... Photoresist, 12 ... Metal film.
Claims (1)
て、該半導体基板上にフォトレジストパターンを形成す
る工程と、該フォトレジストパターンを完全に含むごと
くポリイミド膜パターンを形成する工程と、該ポリイミ
ド膜上を含む前記半導体基板上に金属膜を形成する工程
と、該ポリイミド膜パターン及び該フォトレジストパタ
ーンを同一工程にて除去する工程とを含むことを特徴と
する半導体装置の製造方法。1. A process of forming a wiring pattern on a semiconductor substrate, the process of forming a photoresist pattern on the semiconductor substrate, the process of forming a polyimide film pattern so as to completely include the photoresist pattern, and the polyimide film. A method of manufacturing a semiconductor device, comprising: a step of forming a metal film on the semiconductor substrate including the above; and a step of removing the polyimide film pattern and the photoresist pattern in the same step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221093A JPH0611078B2 (en) | 1986-09-19 | 1986-09-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221093A JPH0611078B2 (en) | 1986-09-19 | 1986-09-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6376458A JPS6376458A (en) | 1988-04-06 |
| JPH0611078B2 true JPH0611078B2 (en) | 1994-02-09 |
Family
ID=16761379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61221093A Expired - Lifetime JPH0611078B2 (en) | 1986-09-19 | 1986-09-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611078B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181031A (en) * | 1983-03-30 | 1984-10-15 | Fujitsu Ltd | Forming method of aerial wiring |
-
1986
- 1986-09-19 JP JP61221093A patent/JPH0611078B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6376458A (en) | 1988-04-06 |
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