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JPH0546972B2 - - Google Patents
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JPH0546972B2 - - Google Patents

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Publication number
JPH0546972B2
JPH0546972B2 JP17827487A JP17827487A JPH0546972B2 JP H0546972 B2 JPH0546972 B2 JP H0546972B2 JP 17827487 A JP17827487 A JP 17827487A JP 17827487 A JP17827487 A JP 17827487A JP H0546972 B2 JPH0546972 B2 JP H0546972B2
Authority
JP
Japan
Prior art keywords
mesa
layer
material layer
etching
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP17827487A
Other languages
Japanese (ja)
Other versions
JPS6421928A (en
Inventor
Koji Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17827487A priority Critical patent/JPS6421928A/en
Publication of JPS6421928A publication Critical patent/JPS6421928A/en
Publication of JPH0546972B2 publication Critical patent/JPH0546972B2/ja
Granted legal-status Critical Current

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  • Led Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

一般に、LED等の光半導体装置の発光特性を
向上するために、選択的にメサエツチングされた
半導体装置のメサ平坦部の形状とその上のオーミ
ツク電極の形状とが一致するように選択的に形成
する必要がある。
Generally, in order to improve the light emitting characteristics of optical semiconductor devices such as LEDs, the mesa is selectively formed so that the shape of the mesa flat part of the selectively mesa-etched semiconductor device matches the shape of the ohmic electrode thereon. There is a need.

第3図a〜cは従来の半導体装置の製造方法を
説明するための工程順に示した半導体チツプの断
面図である。
3a to 3c are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

第3図aに示すように、InP基板1の表面を覆
つてホトレジスト層3dを形成する。
As shown in FIG. 3a, a photoresist layer 3d is formed covering the surface of the InP substrate 1. As shown in FIG.

次に、ホトリソグラフイ技術により選択的にホ
トレジスト層3dに輪状の開孔部4cを設ける。
Next, a ring-shaped opening 4c is selectively formed in the photoresist layer 3d by photolithography.

次に、等方性のウエツトエツチングによりInP
基板1をエツチングしてメサ平坦部6と、ホトレ
ジスト層3dの開孔部近傍にアンダーカツトを生
ずるようにメサエツチ部5を形成する。
Next, InP is etched by isotropic wet etching.
The substrate 1 is etched to form a mesa flat part 6 and a mesa etch part 5 so as to create an undercut near the opening in the photoresist layer 3d.

次に、第3図bに示すようにホトレジスト層3
dを剥離した後、InP基板1の前面にCrとAuの
二重層から成るオートミツク接触性のCrAu層1
2を被着する。
Next, as shown in FIG. 3b, a photoresist layer 3 is applied.
After peeling off the InP substrate 1, an automic contact CrAu layer 1 consisting of a double layer of Cr and Au is placed on the front surface of the InP substrate 1.
2.

次に、第3図cに示すようにホトレジスト層3
eをCrAu層12の上に設けた後、オートミツク
電極を形成したいメサ平坦部6に対応する部分に
のみホトレジスト層3eを残し、次にウエツトエ
ツチングにより、他の部分のCrAu層12をエツ
チングし、最後に、ホトレジスト層3eを除去し
てメサ平坦部6の表面にオーミツク電極12aを
形成する。
Next, as shown in FIG. 3c, a photoresist layer 3
After forming the photoresist layer 3e on the CrAu layer 12, the photoresist layer 3e is left only in the part corresponding to the mesa flat part 6 where the automic electrode is to be formed, and then the CrAu layer 12 in other parts is etched by wet etching. Finally, the photoresist layer 3e is removed to form an ohmic electrode 12a on the surface of the mesa flat portion 6.

第4図は第3図cに対応する半導体チツプの斜
視図である。
FIG. 4 is a perspective view of the semiconductor chip corresponding to FIG. 3c.

第3図cは第4図のA−A′線断面図に相当す
る。
FIG. 3c corresponds to the sectional view taken along line A-A' in FIG.

メサ平坦部6は露出部6aを残してオーミツク
電極12aに覆われている。
The mesa flat portion 6 is covered with an ohmic electrode 12a, leaving an exposed portion 6a.

この方法においてメサ平坦部6の両側の表面の
露出部6aを生じないようにするためには、ホト
レジスト層3eのマスクバタース形状をメサ平坦
部6の平面形状に一致させる必要がある。
In order to avoid exposing the surfaces 6a on both sides of the mesa flat portion 6 in this method, it is necessary to match the mask butter shape of the photoresist layer 3e to the planar shape of the mesa flat portion 6.

このため、ウエツトエツチングの程度が半導体
ウエーハの製造ロツトにより異るのでホトレジス
ト層3e形成のための露光マスクを多種類用意し
て対応している。
For this reason, since the degree of wet etching varies depending on the production lot of semiconductor wafers, many types of exposure masks for forming the photoresist layer 3e are prepared.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置の製造方法は、メサ
平坦部の形状がエツチング程度やウエーハの製造
ロツトによりばらつくので、ホトレジスト層を形
成のため多数の露光マスクを用意しなければなら
ない事、露光前に必らずメサ平坦部の形状寸法を
測定しなければならない事、また露光マスクの目
合わせに高い精度が必要な事等の問題があつた。
In the conventional semiconductor device manufacturing method described above, the shape of the mesa flat portion varies depending on the degree of etching and the production lot of wafers, so it is necessary to prepare a large number of exposure masks to form the photoresist layer, and it is necessary to prepare many exposure masks before exposure. There were problems such as the need to measure the shape and dimensions of the mesa flat part and the need for high accuracy in aligning the exposure mask.

本発明の目的は、完全にオートミツク電極に覆
われたメサ平坦部を有する半導体装置の製造方法
に関する。
The present invention relates to a method of manufacturing a semiconductor device having a mesa flat portion completely covered with an automic electrode.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、 A 半導体基板の一主面の全面にオーミツク電極
となる導電層を形成する工程、 (B) 前記導電層の表面にエツチング・マスクとな
る物質層を形成した後、ホトリソグラフイ技術
により選択的に前記物質層に開孔部を形成する
工程、 (C) 前記開孔部を除く前記物質層をマスクとして
等方性エツチングして、前記導電層に覆われた
前記半導体基板にメサ平坦部と前記開孔部の近
傍にアンダーカツトを生ずるようなメサエツチ
部とを形成する工程、 (D) オーミツク電極を形成すべき前記メサエツチ
平坦部上の前記導電層の上のみ前記物質層を残
し、他の前記物質層を除去し、該残した物質層
をマスクとして前記導電層をエツチングする工
程、 (E) 前記物質層を除去する工程、 を含んで構成されている。
The method for manufacturing a semiconductor device of the present invention includes the following steps: A. Forming a conductive layer to serve as an ohmic electrode on the entire surface of one principal surface of a semiconductor substrate; (B) Forming a material layer to serve as an etching mask on the surface of the conductive layer. (C) isotropically etching the material layer excluding the openings using the material layer as a mask to make the material layer covered with the conductive layer; (D) forming a mesa flat part and a mesa etched part that causes an undercut in the vicinity of the opening part in the semiconductor substrate; (E) removing the material layer, leaving only the material layer, removing the other material layer, and etching the conductive layer using the remaining material layer as a mask; .

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図a〜dは本発明の第1の実施例を説明す
るための工程順に示した半導体チツプの断面図で
ある。
1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

第1図aに示すように、InP基板1の表面に約
200nmのCrAu層2を真空蒸着にて形成し、その
表面にホトレジスト層3aを形成する。
As shown in Figure 1a, approximately
A 200 nm thick CrAu layer 2 is formed by vacuum evaporation, and a photoresist layer 3a is formed on its surface.

次に、ホトレジスト層2に中心線の直径が約
30μmの輪状の開孔部4aを形成した後、CrAu層
2の開孔部4aに露出している部分をエツチング
除去する。
Next, the photoresist layer 2 is coated with a centerline diameter of approximately
After forming the annular opening 4a of 30 μm, the portion of the CrAu layer 2 exposed in the opening 4a is removed by etching.

次に、第1図bに示すように、CrAu層2をマ
スクとしてプロム系のエツチング液を用いてInP
基板1を等方性エツチングをし、開孔部4aの下
に深さ約5μmのメサエツチ部5と平坦部分の直径
が約20μmのメサ平坦部6を形成する。
Next, as shown in FIG.
The substrate 1 is isotropically etched to form a mesa etch portion 5 with a depth of about 5 μm and a mesa flat portion 6 with a flat portion diameter of about 20 μm below the opening 4a.

各メサ平坦部6には、CrAu層2とホトレジス
ト層3aがメサ平坦部6を含めてより広く覆つて
いる。
Each mesa flat portion 6 is covered more widely with the CrAu layer 2 and the photoresist layer 3a, including the mesa flat portion 6.

次に、第1図cに示すように、開孔部4aから
Cr及びAuの各層に対応するウエツトエツチング
液を順次用いて、InP基板1及びホトレジスト層
3aをエツチングマスクとしてCrAu層2のメサ
エツチ部5に面する部分を除去して、自己整合的
にメサ平坦部6の平面形状と同一形状のオーミツ
ク電極2aを形成する。
Next, as shown in FIG. 1c, from the opening 4a
Using a wet etching solution corresponding to each layer of Cr and Au, the portion of the CrAu layer 2 facing the mesa etching portion 5 is removed using the InP substrate 1 and the photoresist layer 3a as an etching mask to flatten the mesa in a self-aligned manner. An ohmic electrode 2a having the same planar shape as the portion 6 is formed.

最後に、第1図dに示すように、ホトレジスト
層3aを剥離する。
Finally, as shown in FIG. 1d, the photoresist layer 3a is peeled off.

ここでは、オーミツク電極2aが完全にメサ平
坦部6を覆うので、従来あつた露出部は無い。
Here, since the ohmic electrode 2a completely covers the mesa flat portion 6, there is no exposed portion that was conventionally present.

第2図a〜eは本発明の第2の実施例を説明す
るための工程順に示した半導体チツプの断面図で
ある。
2A to 2E are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

第2図aに示すように、第1図aに示した工程
でInP基板1の表面を約200nmの厚さのCrAu層
で覆い、その表面にシリコン酸化膜7aを形成す
る。
As shown in FIG. 2a, in the step shown in FIG. 1a, the surface of the InP substrate 1 is covered with a CrAu layer with a thickness of about 200 nm, and a silicon oxide film 7a is formed on the surface.

次に、ホトレジスト技術により直径約25μmの
ホトレジスト層3bを選択的に形成する。
Next, a photoresist layer 3b having a diameter of about 25 μm is selectively formed using a photoresist technique.

次に、第2図bに示すように、ホトレジスト層
3bをマスクとし、シリコン酸化膜7aを選択的
にエツチングして直径が約25μmのシリコン酸化
膜7bを形成したのち、ホトレジスト層3bを剥
離する。
Next, as shown in FIG. 2b, using the photoresist layer 3b as a mask, the silicon oxide film 7a is selectively etched to form a silicon oxide film 7b having a diameter of about 25 μm, and then the photoresist layer 3b is peeled off. .

次に、全表面にホトレジスト層3cを形成した
後、このホトレジスト層3cに選択的にシリコン
酸化膜7bと同心の直径30μmの円周に沿つて開
孔部4bを設け、露出したCrAu層2をエツチン
グ除去する。
Next, after forming a photoresist layer 3c on the entire surface, an opening 4b is selectively provided in the photoresist layer 3c along a circumference of 30 μm in diameter concentric with the silicon oxide film 7b, and the exposed CrAu layer 2 is Remove by etching.

次に、第2図cに示すように、CrAu層2をメ
スクとしてIn基板1をブロム系エツチング液によ
り等方性エツチして深さ5μmのメサエツチ部5と
直径が約20μmのメサ平坦部6を形成する。
Next, as shown in FIG. 2c, using the CrAu layer 2 as a mask, the In substrate 1 is isotropically etched using a bromine-based etching solution to form a mesa etch portion 5 with a depth of 5 μm and a mesa flat portion 6 with a diameter of about 20 μm. form.

次に、第2図dに示すように、In基板1とシリ
コン酸化膜7bをエツチングマスクとして、
CrAu層2に対応するエツチング液を用いてウエ
ツトエツチングし、直径が約20μmのオーミツク
電極2aを形成する。
Next, as shown in FIG. 2d, using the In substrate 1 and the silicon oxide film 7b as an etching mask,
Wet etching is performed using an etching solution suitable for the CrAu layer 2 to form an ohmic electrode 2a having a diameter of about 20 μm.

ここで、メサ平坦部6の直径20μmよりもシリ
コン酸化膜7bの直径が25μmと長いので、オー
トミツク電極2aはInP基板1と自己整合的に形
成され、メサ平坦部6の円形状と同一形状とな
る。
Here, since the diameter of the silicon oxide film 7b is 25 μm, which is longer than the diameter of the mesa flat portion 6, which is 20 μm, the automic electrode 2a is formed in self-alignment with the InP substrate 1, and has the same circular shape as the mesa flat portion 6. Become.

本実施例では、任意のメサ平坦部6にオーミツ
ク電極6を設ける事ができる利点がある。
This embodiment has the advantage that the ohmic electrode 6 can be provided on any mesa flat portion 6.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、選択的にメサエ
ツチングされた、半導体装置をエツチング・マス
クとしてオートミツク電極を形成する事により、
メサ平坦部を完全に覆う形状のオーミツク電極を
有する半導体装置の製造方法を得る効果がある。
As explained above, in the present invention, by forming an automic electrode using a selectively mesa-etched semiconductor device as an etching mask,
This has the effect of providing a method of manufacturing a semiconductor device having an ohmic electrode shaped to completely cover the flat part of the mesa.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜dは本発明の第1の実施例を説明す
るための工程順に示した半導体チツプの断面図、
第2図a〜eは本発明の第2の実施例を説明する
ための工程順に示した半導体チツプの断面図、第
3図a〜cは従来の半導体装置の製造方法を説明
するための工程順に示した半導体チツプの断面
図、第4図は第3図cに対応する半導体チツプの
斜視図である。 1……InP基板、2……CrAu層、3a,3b,
3c……ホトレジスト層、4a,4b……開孔
部、5……メサエツチ部、6……メサ平坦部、6
……露出部、7a,7b……シリコン酸化膜。
1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention;
2A to 2E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention, and FIGS. 3A to 3C are steps for explaining a conventional method for manufacturing a semiconductor device. 4 is a perspective view of the semiconductor chip corresponding to FIG. 3c. 1...InP substrate, 2...CrAu layer, 3a, 3b,
3c... Photoresist layer, 4a, 4b... Opening part, 5... Mesa etched part, 6... Mesa flat part, 6
...Exposed portion, 7a, 7b...Silicon oxide film.

Claims (1)

【特許請求の範囲】 1 (A) 半導体基板の一主面の全面にオーミツク
電極となる導電層を形成する工程、 (B) 前記導電層の表面にエツチング・マスクとな
る物質層を形成した後、ホトリソグラフイ技術
により選択的に前記物質層に開孔部を形成する
工程、 (C) 前記開孔部を除く前記物質層をマスクとして
等方性エツチングして、前記導電層に覆われた
前記半導体基板にメサ平坦部と前記開孔部の近
傍にアンダーカツトを生ずるようなメサエツチ
部とを形成する工程、 (D) オーミツク電極を形成すべき前記メサエツチ
平坦部上の前記導電層の上にのみ前記物質を残
し、他の前記物質層を除去し、該残した物質層
をマスクとして前記導電層をエツチングする工
程、 (E) 前記物質層を除去する工程、 を含むことを特徴とする半導体装置の製造方法。
[Claims] 1. (A) A step of forming a conductive layer to serve as an ohmic electrode over the entire surface of one principal surface of a semiconductor substrate; (B) After forming a material layer to serve as an etching mask on the surface of the conductive layer; , selectively forming openings in the material layer by photolithography; (C) isotropically etching the material layer excluding the openings as a mask to remove the material covered with the conductive layer; (D) forming a mesa flat part and a mesa etched part that causes an undercut in the vicinity of the opening part in the semiconductor substrate; a step of etching the conductive layer using the remaining material layer as a mask; (E) a step of removing the material layer; and (E) removing the material layer. Method of manufacturing the device.
JP17827487A 1987-07-16 1987-07-16 Manufacture of semiconductor device Granted JPS6421928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17827487A JPS6421928A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17827487A JPS6421928A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6421928A JPS6421928A (en) 1989-01-25
JPH0546972B2 true JPH0546972B2 (en) 1993-07-15

Family

ID=16045606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17827487A Granted JPS6421928A (en) 1987-07-16 1987-07-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6421928A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240014519A (en) * 2021-07-02 2024-02-01 에이엠에스-오스람 인터내셔널 게엠베하 Optoelectronic semiconductor device, array of optoelectronic semiconductor devices, and method of manufacturing the optoelectronic semiconductor device

Also Published As

Publication number Publication date
JPS6421928A (en) 1989-01-25

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