JPH0611194B2 - Digital frequency discriminator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital frequency discriminator suitable for a speed control system that controls the rotation speed of a rotating body (or a motor).

Configuration of Conventional Example and Problems Thereof In order to control the rotation speed of the rotating body to be constant, a frequency generator (hereinafter referred to as FG) for detecting the rotation frequency of the rotating body.
Outputs (FG signals) of G (magnetic, optical, electrostatic, etc.) are frequency discriminated, and F is applied to the discrimination reference period T _S.
A speed control method is adopted in which feedback control is performed so that the cycle T _{FG of the} G signal is matched.

Generally, the FG is configured to obtain a position detection pulse equal to the number of teeth Z per one rotation of the rotating body, and its mechanical accuracy determines the detection accuracy. Therefore, when a speed control loop is formed by using an FG with low accuracy, it is necessary to sufficiently reduce the response characteristic of the loop to prevent the occurrence of rotational unevenness, and therefore it is considered that the disturbance such as load fluctuation is weak. Was becoming.

In addition, the size and weight of VTRs have been remarkably reduced in recent years. As a result, the subtotal and weight of the motor itself have to be reduced, the moment of inertia becomes smaller, and the generated torque becomes weaker. It tends to be cheaper. Further, the magnetic tape phase speed must be made extremely low in combination with the high density recording of the VTR, and the stability at the super low speed rotation must be ensured, which is a disadvantageous condition for the motor. In order to overcome these disadvantageous conditions, it is necessary to increase the number of teeth Z of the FG, perform fine rotational position detection, enhance the response characteristics of the speed control loop, and form a loop strong against load fluctuations. However,
When the motor is downsized, the number of teeth Z of the FG is physically restricted. Even if the number of teeth Z can be increased, it is extremely difficult to obtain a machine with high mechanical accuracy. Had become the neck of.

FIG. 1 shows an operation waveform diagram of frequency discrimination in a conventional speed control system. For such frequency discrimination, a digital method with excellent cost performance is adopted regardless of changes in temperature and humidity, changes over time, and the like. One cycle of FG signal S1
The number of clock pulses existing in T _{FG is} counted by a binary counter, an equivalent trapezoidal wave signal S2 is formed, and the discrimination output S3 (DA conversion display) is digitally detected. Here, the cycle error ΔT _FG due to the accuracy of the FG signal S1
If so, the discrimination output S3 changes with respect to the operation center level as shown (enlarged view) during one rotation of the motor.
Therefore, if there is a change in the discrimination output based on the FG detection error, the response of the speed control loop cannot be improved, and even if the number of FG teeth is increased, the frequency of the F signal S1 can be set high. It ends in meaning.

FIG. 2 is a structural example of a conventional digital frequency discriminator, and FIG. 3 is a discrimination operation waveform diagram thereof.

In FIG. 2, reference numeral 1 denotes a timing pulse generation circuit, which receives the FG signal S1 and the clock pulse S4,
The latch pulse S5, the preset pulse S6, and the latch pulse S are synchronized with the rising or falling of the FG signal S1.
In order that the latch operation by 5 can be performed normally, the inhibit clock pulse S7 which inhibits the clock pulse S4 is generated and output so that the m-bit binary counter 2 stops the counting operation at least in the latch period. 4 is 2
It is a first decoder which decodes a predetermined count value NF of the advance counter 2 and obtains a stop control signal S8 for closing the clock gate 3. 5 is the lower n bit output S of the binary counter 2.
9 is derived from the n-bit gate 6 and is a second decoder for giving an equivalent trapezoidal wave characteristic to the n-bit gate 6 and configured to decode the count output of the binary counter 2. The output S2 of the n-bit gate 6 is led to a latch circuit 7 and latched by a latch pulse S5 to obtain a binary discriminant output S3, D
Output S digital-to-analog converted by A conversion circuit 8
Get 10. On the other hand, in order to set the discrimination reference cycle T _S as the discriminator, that is, the discrimination reference frequency _s , the output S11 (preset value NP) of the ROM & decoder 10 is set by the preset circuit 9 by the preset pulse S6 to the binary counter 2
To preset. The mode command signal S12 is input to the ROM & decoder 10 to select the output data NP of the ROM. Needless to say, the preset to the binary counter 2 can selectively control the set input and the reset input of the flip-flop with set / reset that configures the binary counter 2 for each bit.

With the above configuration, the preset value NP is set as shown in FIG. If the center count value 2 ^(n-1) of the lower n bits of the binary counter 2 is the operation center, the preset value NP
Is Set to the value calculated by the formula. Here, _CK is the frequency of the clock pulse S4, _S is the discrimination reference frequency, α
Is a constant value and is the number of clock pulses S4 corresponding to the clock inhibition period and the preset period of the latch value.

In the digital frequency discriminator having such a configuration, if the FG signal S1 as an input signal has a period error ΔT _FG as described above, it is faithfully discriminated. Therefore, the fluctuation of the discrimination output is unavoidable and the speed control system has The responsiveness cannot be increased.

An object of the present invention is to eliminate an input signal S1 which eliminates the problems of the conventional example.
It is an object of the present invention to provide a digital frequency discriminator that is not affected by the periodic error of.

According to the present invention, there is provided frequency discriminating means for discriminating the frequency of an input signal, and storage means for storing the output of the frequency discriminating means.
Compensating means for compensating the reference frequency of the frequency discrimination of the frequency discriminating means by the output of the storing means, storing the discrimination output obtained by the frequency discriminating means in the storing means, and using the output of the storing means The correcting means controls the frequency discriminating means to correct the reference frequency of the frequency discriminating, and the period error ΔT of the input signal.
_It enables stable frequency discrimination independent of _FG .

Description of Embodiments FIG. 4 is a waveform diagram for explaining the basic principle of the present invention. In FIG. 4, S1a is a regular FG signal, S1b
Is an irregular FG signal with a period error ΔT _FG , and S
13 is a waveform in which the counting operation of the m-bit binary counter which constitutes the frequency discriminator is DA converted and displayed, and S2 is the equivalent of the output of the lower n bits of the binary counter, which has a trapezoidal wave characteristic. It is the waveform which carried out DA conversion display of the trapezoidal wave signal. As shown in the waveform S13, in the conventional example, the preset value NP ₀ calculated by the equation (1) is used for the m-bit binary counter.
After presetting, the clock pulse is counted, and when the predetermined count value NF (here, the case where the m-bit output of the binary counter is all "0") is reached, the counting is stopped and The n-bit output is given a trapezoidal wave characteristic and is gate-outputted to obtain an equivalent trapezoidal wave signal of waveform S2.
Then, the count value 2 ^(n-1) of the lower n bits is set to the operation center value NC.
Then, the period from the preset to the operation center value is determined as the discrimination reference period T _S (= 1 / _S ). As described above, there is actually a clock inhibition during the latch operation, but it will be omitted here for the sake of description. Therefore, the regular FG signal S1a
When is input to the discriminator, the discriminant output is equal to the operation center value NC. However, when the irregular FG signal S1b having the periodic error ΔT _FG is input, the discriminant output NE is obtained. , ΔT _FG, which is a value deviated from the central value NC by an amount corresponding to ΔT _FG , and appears as a variation in the discrimination output as shown in the conventional example.

Therefore, in the present invention, this discrimination output NE is stored in a memory circuit (memory) of n bits and Z words, and thereafter the discrimination reference period T _S is corrected by this memory output. More specifically, the operation center value N is at least stored in the memory.
The inverted output NC having a fixed value corresponding to C is first preset in the binary counter (1st preset), and after the 1st preset, the lower n bits of the binary counter are all “0”.
Is detected and this detection output is used to
Preset the OM value (2nd preset). Then, when the storage operation is completed, 1s is set at a desired timing.
The t preset value NC is switched to the memory content NE (similarly, an output obtained by inverting the NE may be used, and this may be performed in the path from detection to presetting). At this time, the memory contents NE are rotated and output in a form shifted by one word each. For example, the first word is the Z word,
The second word is the first word, and the Z word is (Z-
1) Each word is output. If you do this,
The above-mentioned cycle error ΔT _FG can be corrected during presetting. Here, NP ₁ shown in the waveform S13 is the 1st preset value, NP ₂
Is a 2nd preset value, the upper bits of NP ₁ (n +
In 1) to m, at least one bit is "1", and the content of the lower n bits may be NC or NE, and only the lower n bits have meaning. However, actually, the configuration is simpler when the upper bit value of NP ₂ is used, and only in this case, the values of the 1st preset and the 2nd preset may be reversed. 2nd preset value NP ₂ is _Ck is the clock frequency, _s is the discrimination reference frequency (= 1 / T _s ), α ₁ is the first constant value, and 1
The number of clock pulses corresponding to the clock inhibition period and the preset period at the time of latching st preset is α ₂ is the second
Is a constant value and is the number of clock pulses corresponding to the preset period of the 2nd preset.

The stepwise steps in the waveform S13 indicate the counting operation of the (n + 1) th bit of the binary counter. Although the binary counter has been described as the down counter by way of example, it may be an up counter.

FIG. 5 shows an example of one specific configuration of the present invention based on the basic principle of FIG. The difference from the conventional example of FIG. 2 is that a memory control circuit 11, a memory circuit (memory) 12, a third decoder 13 and a switch circuit 14 are newly added. Therefore,
Since the basic operation of the frequency discrimination is the same as that of the conventional example, the description thereof will be omitted and the characteristic feature of the present invention will be described. Here, a timing pulse generation circuit 1, an m-bit binary counter 2,
Clock gate 3, first decoder 4, second decoder 5,
The n-bit gate 6, the latch circuit 7, the preset circuit 9 and the ROM & decoder 10 are frequency discriminating means, the memory circuit (memory) 12, the memory control circuit 11 and the timing pulse generating circuit 1 are memory means, and the third decoder 13 is provided. ，
The switch circuit 14 and the timing pulse generation circuit 1 constitute a correction means.

In FIG. 5, the FG signal S1 is sent to the memory control circuit 11.
Is input and the frequency is divided to generate an address signal S14 for word selection equal to the number of teeth Z of the FG. Memory 1
An address signal S14, a write / read signal S1, a latch pulse S5, and an n-bit digital discrimination output S3 are input to 2, and the write / read signal S15 is set to "H" (or "L") at the time of memory writing. , The digital discrimination output S3 is sequentially stored in each word designated by the address signal S14 by the latch pulse S5. Then, at the time of writing to the memory, a constant value NC which is the same value as the above-mentioned count value NC is output to the memory output S1.
6 Next, at the time of memory read, the write read signal S1
5 is set to "L" (or "H") and latch pulse S5
The memory operation by is canceled, the memory content NE is rotated in place of the constant value NC, and each word is output in the form shifted by one word. For example, the 1st word is the Zth word and 2
The first word is the word, and the Z-word is (Z-
1) Each word is output. This can be easily done by shifting the address signal S14. On the other hand, the lower n-bit output S9 of the binary counter 2 is output by the third decoder 13.
Is decoded, and when the lower n-bit output S9 is all "0", a decoded output S17 is obtained. This decode output S17
Is input to the timing pulse generation circuit 1, the first pulse after the 1st preset is extracted to create a pulse S17a for the 2nd preset, and is output as a preset pulse S6 subsequent to the pulse S6a for the 1st preset. In addition, the preset value of the lower n bits is set to NC or NE in the 1st preset and R in the 2nd preset.
A preset value switching signal S18 for the OM value is created. This preset value switching signal S18 is sent to the switch circuit 14.
And the output S16 of the memory 12 and the lower n bits of the output S11 of the ROM 10 are input, and switched and output as described above. Here, of the output S11 of the ROM 10, (n +
The upper bit outputs of 1) to m indicate a configuration in which they are always output without switching. Therefore, as described above, 1s
Even if the preset values of the lower n bits are exchanged between the t preset and the 2nd preset, they can function normally.

FIG. 6 shows the above operation waveforms. Also, the seventh
The figure shows a divided waveform diagram of the FG signal S1 of the memory control circuit 11,
FIG. 8 shows a rotation circuit 1 for the address signal S14.
A specific example is shown.

FIG. 7 is an operation waveform in which the F signal S1 when the number of FG teeth Z is 8 (Z = 8) is divided to generate divided outputs S1a, S1b, 81c, and these outputs are decoded. The address signal S14 can be generated by Here, (A) shows a case where only the FG signal S1 is simply divided. In this case, for example, when the motor is stopped halfway and is rotated again, the mechanical position and frequency division of the FG are performed. The output relationship changes with a probability of 1 / Z, and the address goes wrong, so it is necessary to write to the memory each time. (B) eliminates this inconvenience, and uses a position detection signal (PG signal) S19 representing one rotation of the FG. If the initial state of the frequency dividing circuit is set by the PG signal S19 by setting or resetting, the address error as in (A) does not occur. (C) is FG signal S1 and PG signal S
19 is used as a signal S20 that is a composite of three levels, and a PG signal S19 is formed at "H" to "M" (intermediate value) levels and an FG signal S1 is formed at "M" to "L" levels. To do. Such a composite signal S20 is possible with a binary level, and for example, the duty ratio of "H" and "L" of the FG signal S1 in one rotation is different from the duty ratios of the other (Z-1) cases by one. This is possible by using the FG thus configured. When the composite signal S20 is used, separation is necessary, and as a result, it serves the same purpose as (B). When the circuit power is turned off, it is necessary to always write to the memory after the power is turned on, except for using a non-volatile writable / readable memory.

FIG. 8 shows an example of a specific circuit for performing the rotation shift when switching from the memory writing to the memory reading in the memory 12 described above, which is performed at the input portion of the address signal S14. That is, a pair of analog switches SA and SB is provided at each address, and the write / read signal S1
By switching SA (1) -SA (Z), SB (1) -SB (Z) by 5, the address signal input iN (1), iN (2),
iN (3), ………… iN (Z-1), iN (Z) address signal output Ou
(1), Ou (2), Ou (3) ………… Ou (Z-1), Ou (Z),
Input at writing iN (Z), iN (1), iN (2), ……… iN (Z-1)
, Ou (1), Ou (2), Ou (3) ......... Ou (Z) can be used for address shift, and the memory contents can be read forward by one word. On the contrary, when the circuit connection of FIG. 8 is changed to read iN (2), iN (3), iN (4),
..., iN (Z), iN (1) address signal output Ou (1),
Ou (2), Ou (3), ... Ou (Z-1), Ou (Z),
IN (1), iN (2), iN (3), ..., iN (Z-
1), iN (Z) are output as address signals Ou (1), Ou (2), O
It is also possible to perform address shift as u (3), ..., Ou (Z-1), Ou (Z) and shift the memory contents forward by one word.

Reference numeral 15 is an inverter that inverts the write / read signal S15.

In the above description, an example in which all bits of the digital discrimination output S3 are stored in the memory is shown. However, when the FG signal S1 having high FG accuracy and small cycle error ΔT _FG is used,
It is also possible to store only the desired lower bit of the n bits of the discrimination output S3 in the memory and share the upper bit of NC with the upper bit to reduce the memory content. Further, instead of providing the rotation circuit shown in FIG. 8 in the memory 12, the memory control circuit 11 may be configured to have a function of performing rotation by shifting the frequency division timing.

The configuration and operation have been described above in detail based on the embodiment,
The digital frequency discriminator of the present invention is a frequency discriminating means (1 to 7, 9 and 10) for discriminating the frequency of an input signal.
And storage means (1 for storing the output of the frequency discrimination means).
2, 11 and 1) and the correction means (13, 14 and 1) for correcting the reference frequency of the frequency discrimination of the frequency discrimination means by the output of the storage means, the discrimination output obtained by the frequency discrimination means. Is stored in the storage means, and the output of the storage means is used to control the frequency discrimination means by the correction means to correct the reference frequency of the frequency discrimination.

EFFECTS OF THE INVENTION As is apparent from the above description, the present invention has a configuration in which the input signal, for example, the FG signal is frequency discriminated, the discrimination output is stored in the memory circuit, and the discrimination reference frequency is corrected by the memory circuit output. , Even if the FG signal includes the periodic error ΔT _FG , the F fluctuation component of the discrimination output can be removed,
It can be applied to a speed control system for controlling the rotation speed of a motor to improve responsiveness, and its practical effect is great. In addition,
It goes without saying that various configurations can be made without departing from the spirit of the present invention.

[Brief description of drawings]

FIG. 1 is an operation waveform diagram of conventional frequency discrimination, FIG. 2 is a block diagram of a conventional digital frequency discriminator, FIG. 3 is an operation waveform diagram of FIG. 2, and FIG. 4 is a basic principle of the present invention. FIG. 5 is a waveform diagram for explaining, FIG. 5 is a block diagram of a digital frequency discriminator of one embodiment of the present invention based on the basic principle of FIG. 4, FIG. 6 is an operation waveform diagram of FIG. 5, and FIG. FIG. 8 is an FG signal divided waveform diagram of the memory control circuit, and FIG. 8 is a rotation circuit diagram of the memory. 1 ... Timing pulse generation circuit, 2 ... m bit of 2
Binary counter, 3 ... Clock gate, 4 ... First decoder, 5 ... Second decoder, 6 ... N-bit gate, 7 ...
... Latch circuit, 8 ... DA conversion circuit, 9 ... Preset circuit, 10 ... ROM & decoder, 11 ... Memory control circuit, 12 ... Storage circuit (memory), 13 ... Third decoder, 14 ... Switch circuit.

Claims (1)

[Claims] 1. A counting means for counting clock pulses, a gate means for taking out the count output of the counting means, a latch means for taking out the output of the gate means by latching it with a latch pulse, and generating a first predetermined value. And a predetermined value generating means for outputting the detection pulse, first detection means for obtaining a detection pulse from the count output of the counting means at a timing representing the first predetermined count value, the latch pulse generated from an input signal, and the latch pulse Timing generating means for creating a first preset pulse that follows later in timing, creating a second preset pulse from the detection pulse, and creating a switching signal with the input signal and the detection pulse And a second predetermined value is output at the time of writing, and the output of the latch means is stored by the latch pulse. Memory means for reading and outputting the stored contents, memory control means for dividing the input signal to generate an address signal and controlling the address of the memory means, and output of the predetermined value generating means by the switching signal. And a switch means for switching between the outputs of the memory means and the output, and outputs of the switch means for the first and second outputs.
And a preset means for presetting the counting means with the preset pulse, and the address value of the address signal of the memory control means is rotated so that the data at the time of writing is output at the timing one before when the memory means is read. A digital frequency discriminator characterized by: