JPH0526434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital phase control device for controlling the phase of a rotating body such as a cylinder, a capstan, or a motor of a magnetic recording/reproducing device (VTR).

Conventional technology In phase control of rotating bodies such as cylinders and capstans in home VTRs, half the frequency of the vertical synchronization signal (3 OHz in the NTSC system) is used as the sampling frequency, as typified by VHS and Beta system VTRs. It is used. Generally, the response of a control system is limited by the sampling frequency, and its upper limit is at most 1/10 of the sampling frequency. That is, when the sampling frequency is 30 Hz, response characteristics can only be provided up to about 3 Hz. This is practically sufficient for stationary VTRs, but for portable 8mm VTRs with built-in cameras, etc., which need to be smaller and lighter,
Considering its structure and usage, it is not necessarily sufficient. That is, similar requirements are placed on the motor itself that drives the rotating body in order to reduce its size and weight, making it susceptible to tape load fluctuations, vibrations, and the like. To solve this problem, for example, frequency generation means (hereinafter referred to as FG)
) to increase the sampling frequency,
This can be achieved by improving the response characteristics of the control system.

Problems to be Solved by the Invention However, with the above configuration, if the mechanical precision of the FG is poor, it will cause rotational phase fluctuations, so a highly accurate FG is required, which is not economical.
There were problems in practical application.

The present invention provides a frequency generating means for detecting the rotational speed of a rotating body, a phase comparing means for comparing the phases of the output of the frequency generating means and a reference signal, a storage means for storing the output of the phase comparing means, and a digital filter that receives the output of the phase comparison means as an input, the output of the digital filter forms a loop for controlling the rotating body, and the writing and reading of the storage means is switched by a mode command signal; The storage means stores the output of the phase comparison means at the time of writing, and provides the read data to the phase comparison means at the time of reading, and the phase comparison means corrects the phase of the reference signal using the data. It is.

Further, the digital phase control device switches the frequency characteristics of the digital filter using a mode command signal, and is set so that the loop response becomes low when writing to the storage means.

Effects According to the present invention, the phase comparison means is configured as described above.
A reference phase corresponding to each FG can be set, and a 1:1 relationship can be established between the FG and the reference phase.
Therefore, a phase comparison output in which the FG mechanical error is corrected can be obtained from the phase comparison means, and the dynamic range can be widened, and the loop response of the phase control system can be set high.

Embodiment FIG. 1 is an electrical block diagram of a digital phase control device showing an embodiment of the present invention. In Fig. 1, 1 is the rotating body, 2 is the FG, 3 is the PG (rotational position detection means), and 4 is the FG signal S _FG of the FG2 and the terminal 5.
input the external reference phase signal S _RF from terminal 6.
7 is a digital phase comparison means that digitally compares the phase using the clock pulse _SCK input from the phase comparison means 4.
8 is a storage means, a readable/writeable memory (RAM) for storing the output _DER of the phase comparator 4, and 9 is a read-only memory (ROM) for storing the output DER of the phase comparison means 4;
A switching means selectively switches the output D _RO of the ROM 7 and the output D _RA of the RAM 8 and supplies it to the phase comparison means 4; 10 is a digital filter that applies digital processing to the output D _ER of the phase comparison means 4; 11 is a digital filter; A driving means for driving the rotating body 1 according to the output D _DF of the digital filter 10, 12 is a PG signal S _PG.
13 is a mode command signal S _MO which takes the FG signal S _FG as input and creates an address signal for RAM8.
In the above configuration, the phase comparison means 4 is constituted by an M-bit binary counter, and obtains the phase comparison output _DER from the lower N bits thereof.

FIG. 2 is a waveform diagram showing an example of the operation of the phase comparison means 4. Waveform A is a reference phase signal, waveform B is a trapezoidal wave signal which is an analog representation of the digital operation of the phase comparison means 4, waveform C is the FG signal _SFG , and waveform D is the phase comparison output _DER . Reference phase signal A is at terminal 5
It is also possible to generate and use an internal reference phase signal by decoding a predetermined count value of a binary counter constituting the phase comparator 4 instead of the external reference phase signal SRF from the external reference phase signal _SRF . The phase comparison means 4 has the function of setting the initial value twice, 1st preset and 2nd preset, and the 1st preset (first initial value setting) is performed with the 1st preset pulse created by the reference phase signal _SRF . After this preset, for example, count down and detect that the lower N bits of the binary counter are all "0", and use this all "0" detection pulse to create a second preset pulse and start the 2nd preset ( Perform the second initial value setting). From then on, the down count continued until the 1st
Set the period from the preset to the count value NH (=2 ^N -1) to a high level NH (=2 ^N -1). Then, for the period from the count value NH to the count value NL (=0), the output of the lower N bits of the binary counter is taken out and a ramp period is set. Further count value NL
The period from to the next 1st preset is set to low level.
Set to NL (=0). The NC of the trapezoidal wave signal B is the center value ^2N-1 of the slope period B.

Here, the preset value at preset is the output D _RA of RAM8 (or
In the 2nd preset, the output D _RO of ROM7 is
The output D _RO of ROM 7 (also the output D _RA of RAM 8) is used. This switching of the preset value is performed by the switching means 9, and the switching signal _SSW is generated by the phase comparing means 4 from the reference phase signal _SRF and the all "0" detection pulse. In addition,
The number of bits of the output _DRA of RAM8 is determined by the phase comparison means 4.
The number of bits of the output _DER is equal to N bits,
Since the binary counter has M bits, the upper M-N bits are not switched by the switching means 9.
ROM7 output _DRO for both 1st and 2nd presets
(MN bits). Also,
When writing to RAM8, the output D _RA is a specific value (=
Fix it to NC-1). Since the output _DRO of the ROM 7 is a fixed value NP, the time Ti from the first preset to the center value NC of the slope is constant, and the point where the reference phase signal _SRF is delayed by Ti becomes the center of phase comparison. Note that the RAM 8 has addresses corresponding to at least the number of teeth of the FG2, and stores the phase comparison outputs D _ER1 to D _ERZ at addresses corresponding to each of the FG2. This writing and address designation are performed by the control means 12.

FIG. 3 is a waveform diagram showing the write operation of the RAM 8, and FIG. 4 is a waveform diagram showing the read operation of the RAM 8. Below, the RAM is shown in Figures 3 and 4.
The operation of the digital phase control device during writing and reading of No. 8 will now be described. Waveforms A to D in FIGS. 3 and 4 are the same signals as waveforms A to D in FIG. 2. Waveform E is PG signal S _PG , waveform F is delayed
PG signal S _PG ', waveform G is address signal of control means 12
_S.A.D. The delayed signal S _PG ′ is, for example, the PG signal S _PG
FG signal S is created by the falling edge of _FG .

In Figure 3, when writing to RAM8, the trapezoidal wave signal B is a certain period of time from the reference phase signal S _RF (waveform A).
Since the center of phase comparison is at the delayed position of Ti, the phase comparison with the FG signal _SFG (waveform C) is performed based on this point. Here, as described above, since FG2 has a mechanical error, the timing at which the FG signal _SFG is generated is also modulated by the mechanical error. Therefore, the phase comparison output _DER has an error pattern as shown in waveform D for each revolution of the rotating body 1.
D _ER1 to D _ER6 occur. This error pattern is detected by the latch pulse S _LA of the phase comparator 4 in the RAM 8.
are stored at addresses AD1 to AD6, respectively. RAM8
The address signal _SAD (waveform G) for selecting an address is created by resetting the count with the delayed PG signal _SPG ' (waveform F) in the control means 12 and dividing the frequency of the FG signal _SFG (waveform C). . During this writing, the frequency characteristics of the digital filter 10 are made low to set the loop response low. In this way, the rotating body 1
Mechanical error of FG2, that is, error pattern D _ER1 ~
Error patterns can be detected with high accuracy without reacting to D _ER6 .

Next, in FIG. 4, when reading the RAM 8, the outputs ER1 to ER6, which are the polarity-inverted outputs of the memory contents D _{ER1 to} D _ER6 of the RAM ₈ , are set as the RAM output D _RA , and the reset operation of the counter in the control means 12 is set to the PG signal S _PG. (Waveform E), and performs a rotation in which the address signal S _AD is shifted forward one address at a time with respect to the writing time. That is, AD1 is AD6, AD2 is
AD1, AD4 to AD3, AD5 to AD4, AD6
Shift each to AD5. In this way, the delay time Ti of the phase comparison means 4 is corrected by the output D _RA ( _ER1 to _ER6 ) of the RAM 8, and the delay times Ti1 to Ti6 corresponding to each of the FG2 can be set.
The obtained phase comparison output _DER is as shown in waveform D.
Mechanical error of FG2, that is, error pattern D _ER1 ~
D _ER6 can be corrected. However, since no FG mechanical error occurs in the output _DER of the phase comparator 4 when reading from the RAM 8, the frequency characteristics of the digital filter 10 are made high to set the loop response high. This allows the response characteristics of the phase control system to be set high regardless of the FG mechanical error.
The performance of the phasic tail device can be improved.

In addition, in the above explanation, the PG signal S _PG is used as a reference,
An example of dividing the frequency of the FG signal S _FG to create the address signal S _AD has been shown, but if the rotational position detection means (PG) 3 is not required, a frequency dividing circuit that divides the frequency of the FG signal S _FG can be provided. It goes without saying that the objective can be achieved in the same way by creating an equivalent PG signal using this frequency dividing circuit and substituting the _PG signal SPG. In addition, when applying the present invention to a VTR etc., a rehearsal function is added to generate the mode command signal S _MO ,
It is desirable to have a configuration in which writing is performed in the RAM 8, and in this case, to prevent load disturbances from being applied to the rotating body 1 as much as possible.

Effects of the Invention As is clear from the above explanation, the present invention detects the mechanical error of the frequency generation means (FG) and stores it in the storage means (RAM), and based on the stored contents, the reference phase of the phase comparison means is determined. Since the configuration is configured to perform correction, it is possible to obtain a phase comparison output that does not include FG mechanical errors, and the response characteristics of the phase control system can be improved, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is an electrical block diagram of a digital phase control device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of the operation of the digital phase comparison means in the same embodiment, and FIG. 3 is a diagram of the same embodiment. FIG. 4 is a waveform diagram showing an example of the RAM write operation in the same embodiment, and FIG. 4 is a waveform diagram showing an example of the RAM read operation in the same embodiment. 1...Rotating body, 2...Frequency generation means, 3...
Rotational position detection means, 4...Digital phase comparison means, 7...Read-only memory, 8...Writing/
Readable memory, 9... switching means, 10... digital filter, 12... control means.

Claims (1)

[Scope of Claims] 1. Frequency generation means for detecting the number of rotations of a rotating body, phase comparison means for comparing the phases of the output of the frequency generation means and a reference signal, and storage means for storing the output of the phase comparison means. and a digital filter whose input is the output of the phase comparison means, the output of the digital filter forming a loop for controlling the rotating body, and the writing and reading of the storage means being switched by a mode command signal. The storage means stores the output of the phase comparison means during writing, provides the read data to the phase comparison means during reading, and the phase comparison means corrects the phase of the reference signal using the data. Features a digital phase control device. 2. The digital phase control device according to claim 1, wherein the frequency characteristics of the digital filter are switched by a mode command signal, and the loop response is set to be low when writing to the storage means.