JPH061451B2 - Memory allocation device for memory cartridge - Google Patents

Description

The present invention relates to a memory allocation device in a system having a removable memory cartridge and arranging the memory of the memory cartridge as a memory bank.

(B) Conventional Technology As disclosed in Japanese Utility Model Publication No. 59-37888, memory cartridges have been conventionally used in electronic devices such as electronic dictionaries, and each memory cartridge has dictionary contents in different languages. By storing the data and exchanging the memory cartridge, it is possible to deal with a plurality of languages.

Further, in a system having a large memory capacity and the memory does not fit in the address space which can be directly accessed by the CPU, as disclosed in Japanese Patent Laid-Open No. 60-33644,
The memory area is expanded by arranging the memory as a bank.

(C) Problems to be solved by the invention For example, in an electronic dictionary, when the dictionary memory contents are large, the conventional bank switching method is used, and the memory of the memory cartridge is stored in the memory bank in the same address space as the internal dictionary memory. It is possible to place it as.

However, in a part of the memory of the memory cartridge,
Identification information indicating the characteristics of each memory cartridge such as a program and dictionary type is stored, and data processing is performed by this program and the program in the electronic dictionary main body, or the identification information is read to determine a data processing execution routine. In the case of the system, as in the conventional system, the bank is simply switched by the bank register, and the program and the identification information in the memory cartridge are referred to each time.
The selection information has to be set in the bank register to switch the memory bank, which is very troublesome.

(D) Means for Solving the Problems In the present invention, a removable memory cartridge having a memory having a first area and a second area is attached to an electronic device, and a part of the address space of the electronic device is provided. In a system in which a memory bank area is provided and the memory is arranged as one memory bank in the area, a bank register in which selection information for selecting a memory bank is set, and a selection signal according to the contents of the bank register are output. A bank decoder, an address decoder which inputs a predetermined bit of an address bus, and which generates an output signal when a predetermined address space other than the memory bank region and narrower than the region is designated, and the bank decoder Input a specific selection signal and the output signal of the address decoder,
A gate circuit for selecting the memory of the memory cartridge when any one of the signals is output, allocating the first area of the memory of the memory cartridge as a bank in the memory bank area, and at the same time, The above problem is solved by allocating an area to the predetermined address space.

(E) Operation In the present invention, not only the bank register and the bank decoder but also the memory bank is selected by the output of the address decoder. Therefore, a part of the memory of the memory cartridge can be directly accessed by the CPU. It is allocated to a predetermined address space other than the area. Therefore, if the above-mentioned program and identification information are stored in this area, these programs and identification information can be stored without setting selection information in the bank register. It becomes possible to refer.

(F) Embodiment FIG. 1 is a block diagram showing the configuration of an electronic dictionary including an embodiment of the present invention. (1) is a CPU, (2) is A _{0 to} A ₁₉ 2
0-bit address bus, (3) D ₀ -D ₇ data bus, (4) 128 KB system ROM storing programs, (5) 256 KB font ROM, (6) RA
M, (7) and (8) are, for example, a 512 KB dictionary ROM 1 and a dictionary ROM 2, (9) which form an internal dictionary such as an English-Japanese dictionary.
Is a removable ROM card in which an address bus, a data bus, and a control line are connected to the main body side by a connector (10). For example, a 512 KB dictionary R that constitutes a Japanese-English dictionary.
It consists of OM3 (11) and dictionary ROM4 (12). Then, the dictionary ROMs (7), (8), (11) and (12) are sequentially allocated as memory banks 0 to 3 on the same address space.

Furthermore, (13) is a memory bank selection circuit,
The bank register (14) to which the bank selection information BK0 and BK1 are set via (3) and the outputs Q ₀ and Q ₁ of the bank register (14) are input to the input terminals A and B, respectively, to obtain the bank selection information. The bank decoder (15) which outputs the corresponding selection signals Y _{0 to} Y ₃ and the addresses A ₁₇ , A ₁₈ and A ₁₉ are input to the input terminals A, B and C, respectively, and the output signals Y _{0 to} Y ₇ are input. And an AND gate (17) for inputting the output signal Y ₀ of the address decoder (16) and the address A ₁₆
And the output signal P of the AND gate (17) and the bank decoder
The OR gate (18) for inputting the selection signal Y ₂ of (15) and the output signals Y _{1 to} Y ₄ of the address decoder (16) are input, and the outputs are connected to the G terminal of the bank decoder (15). And an OR gate (19). The selection signals Y ₀ , Y ₁ and Y ₃ of the bank decoder (15) are supplied to the dictionary ROMs (7), (8) and (12), respectively.
) Chip enable terminal CE, AND gate (20),
(21) and (23), and the output signal R of the OR gate (18) is connected to the chip enable terminal CE of the dictionary ROM (11) through the AND gate (22). .

The AND gates (20) (21) (22) (23) are gates for selecting the dictionary ROM only when the read signal RD is output from the CPU (1).

By the way, the decoders (15) and (16) have the same configuration, and the signal Y ₀ is “1” when the input signals to the input terminals A, B and C are “000” and the signal Y ₀ is “100”. ₁ is "1",
…… When the signal Y ₇ is “1” when it is “111”,
One of Y ₀ to Y ₇ is sequentially set to "1" according to the input signal, and an output is generated only while the signal of "1" is input to the G terminal.

Therefore, in this embodiment, the addresses A ₁₉ , A ₁₈ , and A ₁₇ are
Bank decoder only in the range of "001" to "100"
(15) outputs a selection signal, in which case the bank information BK1,
If BK0 is "00", dictionary ROM (7) is selected,
The dictionary ROM (8) is selected if "01", the dictionary ROM (11) if "10", and the dictionary ROM (12) if "11". That is, as shown in the memory map of FIG. 2, the dictionary ROMs (7) to (12) are assigned to banks 0 and 9 in the same address space 20000H to 9FFFFH of the CPU (1), respectively.
It is allocated as bank 1, bank 2, and bank 3.
Then, the addresses in each bank are designated by the addresses A _{0 to} A ₁₈ . System ROM (4), font RO
M (5) and RAM (6) have memory bank area 20000H
Allocated to an address space other than 9FFFFH.

By the way, in the present embodiment, the address decoder (16) and the AN
The D gate (17) constitutes an address decoder which decodes the upper 4 bits of the addresses A _{16 to} A ₁₉ .
When the addresses A ₁₉ , A ₁₈ , A ₁₇ , and A ₁₆ are “0001”, the output signal P of the AND gate (17) becomes “1”, and the output signal R of the OR gate (18) also becomes “1”. Then, the dictionary ROM (11) of the bank 2 in the ROM card (9) is selected. Here, in the address space of the CPU (1), the addresses A ₁₉ , A ₁₈ , A ₁₇ , and A ₁₆ become “0001” because the area other than the memory bank area is indicated by the shaded area in FIG.
It is an address space of 0H to 1FFFFH, and addresses A ₁₈ , A ₁₇ , A _{16 in} the dictionary ROM (11) of the memory bank 2
The memory area designated by "001" is 90,000H to 9FFFFH indicated by diagonal lines in FIG.

In other words, the ROM of the ROM card (9) ROM (11) 9000
The memory area of 0H to 9FFFFH is allocated to a predetermined address space 10000H to 1FFFFH other than the memory bank area that the CPU (1) can directly access. Therefore, regardless of the contents of the bank register (14),
CPU (1) has a predetermined address 10000H to 1FFFF
If you access H, you can access the dictionary ROM (1
1) 90000H to 9FFFFH can be accessed. Therefore, if programs and identification information are stored in this area of the ROM card (9), the bank register (1
These programs and identification information can be read without performing the setting in 4), and control becomes simple.

For example, as an external program, a subroutine for initialization and a main processing program are stored, and as identification information, information A indicating whether or not the dictionary ROM is correct, information B indicating the presence or absence of the initialization subroutine, and presence or absence of the main processing program are indicated. When the information C is stored and the processing shown in the flowchart of FIG. 3 is to be executed in the system program of the system ROM (4) on the main body side,
Conventionally, the bank register (14) is set to "10" before STEP-1, 3, 5, 7, and 9, and STEP-
In front of 2, 4, 6 and 8, set the bank register (14) to "00".
However, in the present embodiment, these settings are completely unnecessary.

(G) Effect of the Invention According to the present invention, a part of the memory area of the memory cartridge is allocated to a predetermined address space other than the memory bank area that can be directly accessed by the CPU. The contents can be read without setting the selection information in the bank register. Therefore, if the program and various identification information are stored in this partial area, the system program can be simplified. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a memory map in this embodiment, and FIG. 3 is a flow chart showing a concrete example of a system program. (1) ... CPU, (4) ... System ROM, (7) (8) (11) (12) ...
Dictionary ROM, (9) ... ROM card, (13) ... Memory bank selection circuit, (14) ... Bank register, (15) ... Decoder, (1
6) ... Address decoder, (17) ... AND gate, (18) OR
Gate.

Claims (1)

[Claims] 1. A removable memory cartridge having a memory having a first area and a second area is mounted in an electronic device, a memory bank area is provided in a part of an address space of the electronic device, and the memory bank area is provided in the area. In a system in which the memory is arranged as one memory bank, a bank register in which selection information for selecting a memory bank is set, a bank decoder for outputting a selection signal according to the contents of the bank register, and a predetermined bit of an address bus Enter
An address decoder which generates an output signal when a predetermined address space other than the memory bank area and narrower than the area is designated, and a specific selection signal of the bank decoder and an output signal of the address decoder are input. And a gate circuit for selecting the memory of the memory cartridge when any of the signals is output, the first area of the memory of the memory cartridge is allocated as a bank in the memory bank area, and at the same time A memory allocation device for a memory cartridge, wherein the second area is allocated to the predetermined address space.