JPH0616303B2 - General-purpose high-speed processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a general-purpose high-speed processor in which a program memory in a processor is a RAM.

[Conventional technology]

Conventional one-chip high-speed processors are classified as shown in FIGS. 7 to 9 according to the type of memory storing a program. In FIG. 7, a mask ROM (read-only memory) 100 incorporated in the processor 1 serves as a program memory, and in FIG. 8, an external ROM 101 serves as a program memory. A data memory 102 is a RAM (random access memory). D-BUS is a data bus, P-BUS is a program bus, 103 is a controller, 104 is a register, 105 is a shifter, 106
Is a multiplier, and 107 is an ALU for addition and subtraction. FIG. 9 shows a system using an EP-ROM (electrically writable ROM), but since it cannot be directly accessed from the high speed processor 1, an EP-
The program data is transferred from the ROM to the RAM.

In the figure, 1 is a high speed processor (Main CUP) dedicated to digital signal processing, 2 is a high speed memory block, and 3 is a low speed program transfer circuit. A clock generation circuit 11, a reset circuit 12, and a power supply circuit 1 are provided around the CPU 1.
3 and I / O controller 14, etc., and by combining these hardware and the program in the memory block 2,
One signal processing system is configured. This example is mainly used as a program development tool.
/ D (analog / digital) and D / A (digital /
A circuit 15 having each analog conversion function is connected to realize a low-pass filter (LPF) function. CPU
1 and the memory block 2 are connected by a data bus D-BUS and an address bus A-BUS, and a bidirectional bus transceiver 41 and a one-way buffer 42 are interposed between them.

The main memory block 2 has a memory 21 (RAM1)
A memory 22 (RAM2) and a memory controller (decoder) 23 are included. FIG. 10 shows the details of the memory controller 23. The terminals are the write enable WE from the CPU 1 and the terminals are the memory enable M.
EN and the address ADR (H) are input to the terminals. The terminal is the memory enable output EN for RAM1 and RAM2, and the terminal is the write enable output WEN. This memory controller is a simple decoder that switches the selection of RAM1 and RAM2 by the address ADR (H). Table 1 shows this decoding logic.

The program transfer circuit 3 includes a sub memory block 5 and a sub low speed processor 6, and a clock generation circuit 61, a reset circuit 62 and a power supply circuit 63 are provided around the sub memory block 5. A bidirectional bus transceiver 71 is connected to the data bus D-BUS, and a unidirectional buffer 7 is connected to the address bus A-BUS.
2 is intervening. The memory block 5 is the memory 51 (R
In addition to the AM3) and the memory 52 (EP-ROM), an address decoder 53 is provided, and this EP-ROM serves as a storage location for programs.

The operation will be described. When the power circuits 13 and 63 are turned on,
First, the sub CPU 6 starts operation, and the bus transceiver 41 and the buffer 42 between the main CPU 1 and the main memory block 2 are turned off to separate the buses between them.
On the contrary, the bus transceiver 71 and the buffer 72 are turned on to connect the bus on the sub CPU 6 side to the main memory block 2. Then, the sub CPU 6 accesses the memory block 5, and transfers the data read from the EP-ROM (the program executed by the main CPU 1) to the RAM 1 of the main memory block 2. When this is executed up to a predetermined address, the transceiver 71 and the buffer 72 are turned off, and the transceiver 41 and the buffer 42 are turned on instead. Until this time, since the reset control signal R is input from the sub CPU 6 to the reset circuit 12 on the main side, the main CPU 1 is in the reset state and stopped. Then, when the program transfer is completed and the signal R is turned off, the main CPU 1 starts the operation (for example, LPF processing).

[Problems to be solved by the invention]

Since the structure of FIG. 7 can be processed in the chip, it is not necessary to draw out the bus line to the outside, the wiring length of the bus line can be shortened, and it is suitable for high speed operation. However, it is difficult to change the program because it is made into hardware, and the versatility of the processor itself is lost, which is not suitable for small-scale production or program development.

Although the configuration of FIG. 8 can maintain the versatility of the processor itself, the internal bus line must be drawn out of the chip, which increases the wiring length and is disadvantageous in terms of high speed compared to FIG. 7. In addition, since the external ROM is required to have high speed equivalent to the access speed of the processor, EP-R
A memory having a relatively slow access speed such as OM cannot be used and is not suitable for program development.

In the configuration of FIG. 9, the bus line wiring length is long as in FIG. 8 and the high speed is difficult as compared with FIG. 7, but since the program memory is RAM, it is easy to change the program and convenient for program development. Is. However, since the system becomes large, it is difficult to meet the needs of small size and low cost.

The present invention is intended to realize both high speed and versatility by using a RAM as a program memory built in the processor.

[Means for solving problems]

The present invention includes a low-speed memory storing a program outside the chip, a high-speed memory for expanding the program inside the chip, and a function of initializing the program from the low-speed memory to the high-speed memory and a function of executing the program. A general-purpose high-speed processor having a clock generator for switching and outputting a low-speed clock or a high-speed clock, and using the high-speed clock during normal operation, and using the low-speed clock during initialization from the low-speed memory to the high-speed memory The feature is that the speed is made lower than usual, and the details of the configuration and operation will be described with reference to the illustrated embodiment.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 7 are designated by the same reference numerals. This example is also a system in which the program memory is built in the processor 1, but unlike FIG. 7, it is realized by the RAM 110. However, since the RAM is effective, the program memory 1 that uses an EP-ROM externally
11 is provided, and the program is initialized (loaded) from the RAM 11 to the RAM 110. Reference numeral 110 'is a small capacity program ROM storing an initialization program for this purpose. In this way, EP-ROM111
Is slow but the RAM 110 is fast, so that the processor 1 can perform high-speed processing after initialization. In addition, by rewriting the contents of EP-ROM111, R
Since the contents of the AM 110 can be changed, the processor 1 can be made versatile.

However, the high-speed processor 1 directly uses the low-speed EP-ROM 11
In order to make 1 accessible, it is necessary to reduce the operating speed of the processor 1 at the time of initialization as compared with the normal operation. Reference numerals 112 and 113 denote clock control circuits and frequency dividing circuits for this purpose, and FIG. 2 is a detailed view thereof. The clock control circuit 112 is a D type flip-flop FF.
When it is reset by the output of the reset circuit 12, the Q output is set to “0”, the gate G ₁ of the frequency dividing circuit 113 is opened, and the low-speed clock is output from the 1 / an frequency divider.
From this EP-ROM 111 to RAM by this low-speed clock
The program is loaded into 110. Then, the controller 103 when the initialization is completed the flip-flop FF so that the "1" to the clock control output CC open the gate G ₂ to "1" to Q output. As a result, a high-speed clock is output from the 1 / n frequency divider, and the processor 1 can access the program in the RAM 110 at high speed.

3A and 3B are explanatory diagrams of the program memory. FIG. 3A shows the internal memory 110, and FIG. 3B shows the external memory 111. For the internal memory, addresses from △△△ + 1 to □□□ are for programming (R
AM), the program of the external memory (EP-ROM) is initialized here. 00 in internal memory 110
0 to ΔΔΔ are mask ROMs 110 ′ that store this initialization program, and the processor 1 can load the main program from the EP-ROM 111 to the RAM 110 by executing this initialization program after reset. FIG. 4 is a flow chart showing the contents of this initial program.

FIG. 5 shows another embodiment of the present invention, in which the external memories 111 ₁ ...
The program is configured so that n kinds of programs are stored in 111n and one of them can be selected by the switch 112 to be initialized in the internal memory 110. This way,
For example, a fixed tone control circuit can be configured in which filter programs having different attenuation amounts and cutoff frequencies are built in each external memory, and a user can operate a switch to realize arbitrary frequency characteristics.

FIG. 6 shows that the initial program in the program ROM can be accessed without paying particular attention to the external memory by making the addresses of the program memories 110 and 111 continuous. At this time, if the clock is slowed down, it is not necessary to consider the difference in access speed from the internal memory.

〔The invention's effect〕

As described above, according to the present invention, the same processor can be used for various kinds of processing because the versatility of the processor itself can be maintained, and the cost can be reduced due to the effect of mass production. Further, since the low-speed EP-ROM or EEP-ROM can be used as the external memory at the time of development and the ROM can be used after the development, it is possible to reduce the development cost for the small-quantity production and the development period.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed diagram of a clock switching circuit thereof, FIG. 3 is an explanatory diagram of a program memory, FIG. 4 is a flow chart of an initialization program, and FIG. FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 6 is an explanatory diagram showing another example of the program memory, and FIGS. 7 to 9 are block diagrams showing different examples of the conventional processor and the program memory. FIG. 10 is a detailed view of the memory controller of FIG. In the figure, 1 is a processor, 110 is an internal program memory (RAM), 111 is an external program memory, 112,
Reference numeral 113 is a clock switching circuit.

Claims (1)

[Claims] 1. A low-speed memory storing a program is provided outside the chip, a high-speed memory for expanding the program is provided inside the chip, and a function for initializing the program from the low-speed memory to the high-speed memory and the program are executed. A general-purpose high-speed processor having a function, provided with a clock generation means for switching and outputting a low-speed clock or a high-speed clock, and using the high-speed clock during normal operation, and using the low-speed clock during initialization from the low-speed memory to the high-speed memory A general-purpose high-speed processor whose operating speed is lower than normal.