JPH0616531B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having programmable chip functions.

[Technical background of the invention and its problems]

2. Description of the Related Art In recent years, the following LSIs have emerged with the demand for small-quantity and high-mix types of semiconductor integrated circuits.

(1) Standard Cell Method Circuit blocks used in the LSI are registered in advance in a computer, and these circuit blocks are arranged and wired by an automatic process of the computer to obtain a desired final product.

(2) Gate array method The basic circuits constituting the logic gate are arranged and formed in advance on the substrate in an array form, and the wiring pattern is determined on this by automatic wiring similarly to the standard cell method to obtain a desired LSI. .

These have the advantage that the development period is shorter than that of a completely hand-designed LSI. However, even in these methods, a manufacturing process using a lithography technique is required, and there is a problem that it takes several weeks to several months from completion of design to completion of LSI.

On the other hand, the present applicant has previously proposed an LSI system in which the chip function is completely field programmable (Japanese Patent Application No. 58-157718). The basic structure is as shown in FIG. In the figure, circuit blocks 21 ₁ and 2 composed of one or more logic function elements
1 _{2, ...,} 21 _N are built in the substrate in a state that ends the wiring process by techniques previously only IC. A wiring region is provided adjacent to the circuit block region 21, and the signal input wiring group 24 and the signal output wiring group 2 intersect each other in the wiring region.
3 are provided. Each signal input wiring 24 is directly connected to the signal input terminal of the circuit block. Each signal output wiring 23 is connected to a signal output terminal of the circuit block by a branch wiring forming a T-shaped path. Then, the signal output wiring group 23 and the signal input wiring group 2 in this wiring region
At each intersection of 4, there is provided a switch element 22 for connecting the signal output wiring and the signal input wiring, which can electrically write the ON / OFF state. The switch element 22 is, for example, an E ² PROM or a MOSFET including a 1-bit memory.

According to this method, since the function of the chip is field programmable, the user can obtain a desired LSI having a high logic function remarkably quickly by manually writing the logic function by himself / herself. You can Moreover,
An LSI can be designed in a form in which an input signal and an output signal of a circuit block having a certain logic function are connected, and it is easy for a designer who is familiar with the logic design on the board to understand.

In this method, however, one signal input wiring intersects with many signal output wirings via switch elements. When constructing a practical LSI, the number of switch elements connected to one signal input wiring is several hundreds to several hundreds.
It will be 0. When this signal input wiring is activated, only one of these switch elements is in the ON state, and the remaining switch elements are all in the OFF state. This is shown in FIG. 22 ₁ indicates a switch element in the ON state, and other switch elements 22 ₂ ,
22 ₃ , ..., 22 _N are in the OFF state. Reference numeral 31 is an input buffer of the circuit block 21. CM circuit block
When the OS structure is adopted, the input impedance of the input buffer 31 is capacitive as indicated by the capacitor 32. When the switch element has a MOSFET structure, its current-voltage characteristic is as shown in FIG. Switch element is ON
The saturation current Isat in the state is usually preferably several 100 μA. This is the ON current. On the other hand, the switch element is OF
Ideally, the current in the F state is zero, but
In the FET structure, the leakage current I _L flows when it is off. Here, assume the following case. That is, the signal level of the signal output lines 23 ₁ connected to the switching element in the ON state is low (L) level, m-number of signal output lines connected to the other switching elements in an OFF state is at a high (H) level If there is, the input capacitor 32 of the input buffer 31
The current flowing into is m × I _L. Then, the time change of the potential v of the input terminal 33 is v = mI _L t / C. C is the capacitance of the capacitor 32, and t is time.
Therefore, after a sufficiently long time, v becomes H level for the input buffer 31. The level to be transmitted is the potential of the signal output wiring 23 ₁ , that is, the L level. This means that the circuit malfunctions due to the leakage current of the OFF switch element.

As described above, the programmable matrix shown in FIG. 2 is formed by the switch matrix using the switch element having the MOSFET structure.
If the SI is configured, the OFF characteristic of the switch element is not perfect, and thus malfunction easily occurs.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit in which the function of a chip is programmable, which prevents the above-mentioned switch element in the OFF state from malfunctioning due to a leakage current.

[Outline of Invention]

The present invention relates to an LSI in which the function of a chip is programmable by the switch matrix described above, by inserting a resistor between the input terminal of the input buffer to which the signal input wiring of the circuit block is connected and the ground line or the power supply line. , Malfunction by setting the resistance value so that it does not reach the H level even if the leak current of all the switch elements in the OFF state flows, and reaches the H level when the ON current of one switch element flows. Prevent.

〔The invention's effect〕

According to the present invention, the user can change the connection state many times in the field to construct a desired logic LSI, and the conditions required for the characteristics of the switch element used for this are not strict, and the reliability is high. It is possible to obtain a highly programmable LSI. In particular, the present invention is
There are many circuit blocks, that is, the number of OFF switch elements / O
Highly integrated programmable LS with a large number of N switch elements
When applied to I, it exerts a great effect.

Example of Invention

 Examples of the present invention will be described below.

First, the basic layout will be described with reference to FIG. As shown in the figure, a plurality of circuit blocks 2 are provided on one side of the Si wafer.
1 _{1, 21} 2, ..., the circuit block region 21 is built is 21 _N is formed. Each circuit block is composed of one or more logic function elements such as a 4-input NAND gate. This logical function element is, for example, a CMO.
It is an S structure and is a dedicated IC, that is, a handwritten standard cell in the standard cell system or a pre-wired gate array.

A specific configuration example of the circuit block area is as follows.

(1) Block with two 4-input NAND gates ...... 15 (2) Block with four 2-input NAND gates ...... 14 (3) Block with one 8-input NAND gate ...... 1 (4 ) Blocks with four inverters ...... 100 (5) Blocks of 8-bit registers ...... 19 (6) Blocks with two D-type flip-flops ...... 19 (7) Two 4-input AND gates Blocks with 17 (8) Blocks with 4 2-to-1 data selectors ...
... 13 (9) Blocks with two 4-bit binary counters ... 11 (10) Blocks with two 2-4 line decoders ...
7 (11) Block with 3-8 line decoder ...... 3 (12) Block with 2 4-1 selectors ...... 5 (13) Block with 8-1 selector ...... 4 (14) Blocks with 8-bit serial input-parallel input shift register …… 3 blocks (15) Blocks with 8-bit parallel input-serial output shift register …… 3 blocks (16) 8-bit serial input-direct output shift register Block: 2 blocks (17) Block with two monostable multivibrators
…… 4 pieces (18) Block with 4 2-input OR gates….
… 4 (19) Block with 4 2-input NOR gates
…… 3 (20) Block with two AND-OR inverters ……
3 blocks (21) 64-bit RAM block 3 blocks (22) 2 input EXCLUSIVE-OR gates with 4 blocks 2 blocks (23) 4-bit comparator block 3 blocks (24) J -A block with two K flip-flops ...
… 4 (25) 9-bit even / odd parity generator / checker block… 3 (26) 4-bit binary full adder block… 2
Number (27) Block with 4 2-input multiplexers 5 (28) Block with 4 SR latches 2 (29) ALU block 1 (30) 8-bit address Sable latch block ……
1 (31) Look-ahead carry generator block ...... One or more 274 circuit blocks consisting of MSI are formed in the circuit block area 21 so that an LSI of all functions can be created from one type of chip. It has become. Each circuit block has an average input number of 8 and an output number of 4. The input section and the output section of the logic function element are the input section and the output section of the circuit block, and the output section is provided with an output buffer (not shown). The output section is fixedly connected to the signal output wiring 23 so as to form a T-shaped path, and the input section is connected to the output wiring 2
3 are connected to the signal input wirings 24 intersecting with the wirings 3. A switch element 22 is provided at each intersection of the signal output wiring 23 and the signal input wiring 24.
The switch element 22 is, as described above, the E ² PROM or 1
A signal output wiring 2 such as a MOSFET with a bit memory, which electrically controls the switch element 22 from the outside.
3 and the signal input wiring 24 can be connected. That is, the connection of the input / output unit is basically one switch, and the equipotential wiring length associated with one current path is 2.5 l on average when the length of the side of the wiring region is 1.

FIG. 1 shows the configuration of the wiring on the switch matrix, the switch elements, and the input buffer 16 in the circuit block 11 when focusing on one signal input wiring 14. The switch element 12 ₁ is arranged at the intersection of the signal output wiring 13 ₁ and the signal input wiring 14 and connects them, and it is assumed that the switch element 12 ₁ is in the ON state. The other switch elements 12 ₂ , 12 ₃ , ..., 12 _N are arranged at the respective intersections of the remaining signal output wirings 13, ₂ , 13 ₃ , ..., 13 _N and the signal input wiring 14, and these are in the OFF state. Is assumed. Reference numeral 15 denotes a capacitor existing at the input terminal of the input buffer 16 and indicates the sum of the stray capacitance of the input capacitance signal input wiring 14 of the input buffer 16 itself, the junction capacitance of the terminal of the switch element 12, and the like.
Reference numeral 17 denotes a resistor (resistance value R) inserted between the input terminal of the input buffer 16 of the circuit block 11 and the ground line.

Here, the maximum L level of the input buffer 16 is set to V _L (max
), And the minimum H level is V _H (min). The number of switch elements in the OFF state out of the number M of switch elements on the signal input wiring 14 is N = M−1, and the maximum leakage current of these OFF switch elements is I _L (max). The ON switch element on the signal input wiring 14 is only 12 _1.
The N current and _{I ON.} Then, the resistance value R is determined as follows. That is, (1) RNI _L (max) <V _L (max) as a condition that L level can be maintained even if leakage current flows (2) RI _ON > V _H (as a condition that H level is generated when ON current flows) min).

Now, as a specific example, consider a case where the switch element is made of an E ² PROM cell having a gate length of 1 μm and a gate width of 3 μm, and I _L (max) = 100 nA. Further, it is assumed that N = 1000 and V _L (max) = 0.8V V _H (min) = 2.4V considering the TTL level as a logic level. I _ON = 1 mA is possible as the ON current, and assuming this, 2.4 kΩ <R <8 kΩ is obtained from the conditions (1) and (2). By setting the resistance value R in such a range, the circuit operates without malfunction.

Normally, the capacitance of the input capacitor 17 reaches C = 2 pF, so if the resistor 17 is not present, the time change of the rise of the input terminal potential of the input buffer 16 due to the OFF switch element leakage current is v = NI _L t / C = 1000 × 100 (nA) × t / 2 × 10 ⁻¹² (F) = 5 × 10 ⁷ (V / sec) × t, and the potential changes from OV to 0.8V in about 16 nsec. , The circuit cannot operate normally.

As described above, according to this embodiment, it is possible to obtain the programmable LSI capable of ensuring the normal operation even when the switch element in which the leakage current flows when it is turned off is used.

The present invention is not limited to the above embodiment. For example, if there is a buffer whose input impedance is capacitive in the signal path passing through the switch matrix as well as the input terminal of the circuit block, the leakage current of many OFF switch elements will be superimposed and the input terminal of that buffer will Similarly, the potential rises. Therefore, it is preferable to insert a resistor also in the input terminal portion of these buffers.

FIG. 3 shows the configuration of such an embodiment. 31 in the figure
_1, 31 2, _..., 31N is a circuit block, 33 signal output lines, 34 indicates a signal input lines, showing the switch element 32 is placed in these intersections. A resistor 36 is inserted in the input terminal portion of each circuit block 31 as in the previous embodiment. In addition, a buffer 35 is provided in the middle of the signal output wiring 33 for the purpose of waveform shaping and driving capability improvement.
However, the resistor 36 is also inserted in the input terminal portion of the buffer 35. Further, FIG. 3 shows a programmable L
When the SI has a hierarchical structure, that is, a certain circuit block (31 _{3 in the} figure) is a plurality of lower-level circuit blocks 31 ₃
-1,31 _3-2 shows a case composed of ... and switch matrix. In such a case, as shown in the figure, at the same time as inserting the resistor 36 into the input terminal portion of the input buffer of the upper circuit block 31 ₃ , the input terminal of the input buffer 35 of the lower circuit block, for example, 31 ₃ -1. A resistor 36 is also inserted in the part.

This makes it possible to obtain a programmable LSI capable of suppressing a potential rise of a signal passing through the switch matrix in the capacitive buffer and performing a reliable logical operation.

In the above embodiment, the resistor is inserted between the input terminal portion of the buffer circuit and the ground line, but the malfunction can be similarly prevented by inserting the resistor between the input line and the ground line. Also, resistors may be inserted on both the ground line side and the power line side. Furthermore, these resistors need not be in the immediate vicinity of the input terminal of the buffer, and may be provided at any position on the signal line connected to the input terminal of the buffer.

[Brief description of drawings]

FIG. 1 is a diagram showing a main configuration of an LSI of one embodiment of the present invention, FIG. 2 is a diagram showing a basic configuration of the entire LSI, and FIG. 3 is a diagram showing an LSI configuration of another embodiment, Figure 4 is second
FIG. 5 is a diagram for explaining a problem of an input terminal portion of a circuit block in the LSI shown in FIG. 5, and FIG. 5 is a diagram showing current-voltage characteristics of a MOSFET structure switch element. 11 ... Circuit block, 12 (12 ₁ , 12 ₂ , ...) ... Switch element, 13 (13 ₁ , 13 ₂ , ...) Signal output wiring, 14 ... Signal input wiring, 15 ... Input capacitor, 16 ... Input buffer, 17 ... Resistance.

Claims (4)

[Claims] 1. A plurality of circuit blocks, each having a logical function itself and having a signal input portion and a signal output portion, which are built in a substrate, and adjacent to a circuit block region formed by the plurality of circuit blocks. And a wiring region formed on the substrate, the circuit block region is composed of a set of a plurality of types of logic function elements, and the wiring region includes a signal input wiring group and a signal output wiring group that intersect with each other. The signal input wiring group is connected to the signal input section of each circuit block, the signal output wiring group is connected to the signal output section of each circuit block, and these connections are connected to the circuit block. Is performed in the wiring regions adjacent to each other, switch elements are respectively provided at intersections of the signal input wiring group and the signal output wiring group,
By controlling the ON / OFF state of the switch element, the input / output relationship between the circuit blocks is determined and a desired integrated circuit is constructed. The signal input terminal of the circuit block and the ground line or the power supply line. A semiconductor integrated circuit in which a resistor is inserted between and. 2. The semiconductor integrated circuit according to claim 1, wherein the signal input portion of the circuit block has a CMOS structure. 3. The semiconductor integrated circuit according to claim 1, wherein the switch element has a MOSFET structure. 4. A maximum value of a low level of an input signal to a circuit block is V _L (max) and a minimum value of a high level is V _H (min).
), The switch element number of the M maximum leakage current of the switch element exists in the I _{L (max),} one signal input wire,
When the current capacity of the switch element which is _ON is ION, the resistance is R> _VH (min) / _ION and R < _VL (max) / {(M-1) _IL (max)}. The semiconductor integrated circuit according to claim 1, wherein a resistance value R that satisfies the above is set.