JPH0616533B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having programmable chip functions.

[Technical background of the invention and its problems]

2. Description of the Related Art In recent years, the following LSIs have emerged with the demand for small-quantity and high-mix types of semiconductor integrated circuits.

(1) Standard Cell Method Circuit blocks used in the LSI are registered in advance in a computer, and these circuit blocks are arranged and wired by an automatic process of the computer to obtain a desired final product.

(2) Gate array method The basic circuits constituting the logic gate are arranged and formed in advance on the substrate in an array form, and the wiring pattern is determined on this by automatic wiring similarly to the standard cell method to obtain a desired LSI. .

These have the advantage that the development period is shorter than that of a completely hand-designed LSI. However, even in these methods, a manufacturing process using a lithography technique is required, and there is a problem that it takes several weeks to several months from completion of design to completion of LSI.

On the other hand, the present applicant has previously proposed an LSI system in which the chip function is completely field programmable (Japanese Patent Application No. 58-157718). The basic structure is as shown in FIG. In the figure, circuit blocks 1 ₁ , 1 ₂ , which are composed of one or more logic function elements,
..., 1 _N is built in the substrate in a state that ends the wiring process by techniques previously only IC. This circuit block area 1
A wiring region is provided adjacent to the wiring region, and a signal input wiring group 3 and a signal output wiring group 2 which intersect with each other are arranged therein. Each signal input wiring 3 is directly connected to the signal input terminal of the circuit block. Each signal output wiring 2 is connected to a signal output terminal of the circuit block by a branch wiring forming a T-shaped path. Then, at each intersection of the signal output wiring group 2 and the signal input wiring group 3 in this wiring region, an electrically OF, OFF state for connecting the signal output wiring and the signal input wiring is written. A switch matrix is provided by providing switch elements 4 that can be used. The switch element 4 is, for example, an E ² PROM or a MOSFET having a 1-bit memory.

According to this method, since the function of the chip is field programmable, the user can obtain a desired LSI having a high logic function remarkably quickly by manually writing the logic function by himself / herself. You can Moreover,
An LSI can be designed in a form in which an input signal and an output signal of a circuit block having a certain logic function are connected, and it is easy for a designer who is familiar with the logic design on the board to understand.

By the way, in this new method, if it is possible to easily check whether or not the ON / OFF information on the switch matrix is written without fail, it is useful both in the logic design and in the circuit operation check after the design is completed. is there.

[Object of the Invention]

In view of the above points, an object of the present invention is to provide a programmable LSI using a switch matrix, and to provide a semiconductor integrated circuit capable of easily checking ON / OFF information of the switch matrix.

[Outline of Invention]

The present invention provides a circuit for activating the signal output wirings one by one in the LSI in which the chip function is programmable by the above-mentioned switch matrix, and turns on or off the switch elements on the activated signal output wirings. OFF
It is characterized in that a parity check circuit for judging whether the number of states is odd or even is provided.

〔The invention's effect〕

According to the present invention, the switch matrix is turned on and off.
Information can be easily checked, and a programmable LSI useful for logic design and for checking circuit operation after design can be obtained.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a basic layout of a programmable LSI of one embodiment. Parts corresponding to those in FIG. 3 are designated by the same reference numerals as those in FIG. As shown in the figure, a plurality of circuit blocks 1 ₁ , 12 ₂ , ..., 1 _N are formed on one side of the Si wafer to form a circuit block region 1. Each circuit block is composed of one or more logic function elements such as a 4-input NAND gate. The logic function element has, for example, a CMOS structure, and is a dedicated IC, that is, a handwritten standard cell in a standard cell system or a wired gate array. The complex logic function element may be formed by combining various standard cells by interconnection using a standard cell method.

A specific configuration example of the circuit block area is as follows.

(1) Block with two 4-input NAND gates ...... 15 (2) Block with four 2-input NAND gates ...... 14 (3) Block with one 8-input NAND gate ...... 1 (4) ) Blocks with four inverters ... 100 (5) Blocks of 8-bit registers ... 19 (6) Blocks with two D-type flip-flops ... 19 (7) Two 4-input AND gates Blocks with 17 (8) Blocks with 4 2-to-1 data selectors 13 (9) Blocks with 2 4-bit binary counters 11 (10) 2-4 line decoder Blocks with 2 ... 7 (11) Blocks with 3-8 line decoder ... 3 (12) Blocks with 2 4-selectors 5 (13) 8-1 select Block with data ... 4 (14) Block with 8-bit serial input-parallel output shift register ... 3 (15) Block with 8-bit parallel input-serial output shift register ... 3 (16) 8 Block with bit serial input-serial output shift register ...... 2 blocks (17) Block with 2 monostable multivibrator ...... 4 blocks (18) Block with 4 2-input OR gates ...... 4 blocks (19) Block with 4 2-input NOR gates ...... 3 blocks (20) Block with 2 AND-OR inverters 3 blocks (21) 64-bit RAM block 3 blocks (22) 2-input EXCLUSIVE-OR gate 4
Two blocks (23) 4-bit comparator block (3) (24) Two JK flip-flop blocks (4) (25) 9-bit even / odd parity generator / Block of checker …… 3 (26) Block of 4-bit binary full adder …… 2 (27) Block with 4 2-input multiplexers …… 5 (28) With 4 S-R latches Block: 2 blocks (29) ALU block: 1 block (30) 8-bit addressable latch block: 1 block
(31) Look-Ahead Carry Generator Blocks ... One or more 274 circuit blocks consisting of MSI are formed in the circuit block area 1 so that an LSI having all the functions can be produced from one kind of chip. Has become. Each circuit block has an average input number of 8 and an output number of 4. The input section and the output section of the logic function element are the input section and the output section of the circuit block, and the output section is provided with an output buffer (not shown). The output portion is fixedly connected to the signal output wiring 2 so as to form a T-shaped path, and the input portion is connected to the signal input wiring 3 that intersects with the output wiring 2.
A switch element 4 is provided at each intersection of the signal output wiring 2 and the signal input wiring 3 to form a switch matrix. The switch element 4 is, for example, an E ² PROM in which an ON / OFF state can be electrically written under the control of the outside, whereby the signal output wiring 2 and the signal input wiring 3 can be connected. . That is, the wiring of the input / output section basically needs only one switch,
As is apparent from FIG. 1, the equipotential wiring length associated with one current path is 2.5 l on average, where l is the length of the side of the wiring region.

According to the present invention in such a programmable LSI,
A circuit for determining ON / OFF information of the switch matrix is provided. That is, the check bit wiring 5 running parallel to the signal input wiring 3 is provided, and the same switch element 6 as the switch element 4 on the switch matrix is provided at the intersection of this wiring 5 and each signal output wiring 2. Check
A bit switch element array 7 is prepared. The ON / OFF states of the switch elements 6 on the switch element array 7 are set so that the number of ON / OFF states of the switch elements on each signal output wiring 2 is odd or even. That is, O of the switch elements 6 on the switch element array 7
N and OFF are used as check bits. Reference numeral 8 is a parity check circuit, in which the signal input wiring 3 and the check bit wiring 5 are connected in parallel to the input terminal. Reference numeral 9 denotes a circuit for activating the signal output wirings 2 one by one in order to perform the parity check for each signal output wiring 2, which is provided between the circuit block area 1 and the switch matrix. There is.

FIG. 2 shows a specific configuration of the activation circuit 9. The activating circuit 9 is an example using a shift register for sequentially selecting signals output wiring 2 specifically illustrates only the portion corresponding to one circuit block 1 ₁ in FIG. The configurations of the portions corresponding to the other circuit blocks are also repeated. As shown in the figure, the shift register 91
To guide an output terminal 100 of the output terminal and the circuit blocks 1 ₁ to selectively switched terminal 99, the AND gate 9
2, 93, an inverter 94 and an OR gate 95. Reference numeral 96 is a parity check control terminal, 97 is an input terminal of the shift register 91, and 98 is a clock terminal of the shift register 91.

With such a configuration, the desired logical function is to turn ON / OFF the switch elements 4 on the switch matrix as described above.
Programmed by setting F. The switch elements 6 on the check bit switch element array 7 are set so that the number of ON or OFF states of the switch elements on the signal output wiring 2 is odd or even. In the normal logic operation, the control signal supplied to the parity check control terminal 96 is set to "0". As a result, the AND gate 92 is in the prohibition state, the AND gate 93 is in the conduction state, and the output terminal 1 of the circuit block is
The information of 00 passes through the activation circuit 9 and its output terminal 99.
Be transmitted to. In this way, the output signal of each circuit block is supplied to the signal output wiring 2 on the switch matrix,
The desired logical operation is performed. If you want to check the ON / OFF information of the switch matrix,
"1" is given to the check control terminal 96. As a result, the AND gate 92 is turned on and the AND gate 93 is turned off. Then, by inputting "1" to the shift register 91 and sequentially shifting it, "1" is sequentially output to the output terminal 99 of the activation circuit 9, and the signal output wiring 2 on the switch matrix is connected to one. Activate books one by one. "1" is input to the parity check circuit 8 when the switch element on the activated signal output wiring 2 is in the ON state, and "0" is input in the OFF state. In this way, the parity check circuit 8 sequentially determines the odd / even number of ON or OFF states of the switch elements arranged along each signal output wiring 2 to determine whether the ON / OFF information of the switch matrix is correct. It can be determined whether or not.

As described above, according to the present embodiment, it is possible to determine whether or not the ON / OFF information pattern on the programmed switch matrix is correct by adding a relatively simple circuit, thus facilitating logic design. Thus, it is possible to realize a programmable LSI that can easily check the circuit operation after logic design.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the one in which the shift register is built in as the activation circuit for the parity check has been described. Can also be configured to be activated.

Others The present invention can be variously modified and implemented without departing from the spirit thereof.

[Brief description of drawings]

FIG. 1 shows a programmable LSI according to an embodiment of the present invention.
FIG. 2 is a diagram showing a specific configuration of the activation circuit, and FIG. 3 is a diagram showing a layout of a basic programmable LSI according to the prior application. 1 ₁ , 1 ₂ , ..., 1 _N ... Circuit block, 2 ... Signal output wiring, 3 ... Signal input wiring, 4 ... Switch element, 5 ... Check / bit wiring, 6 ... Check・
Bit switch elements, 7 ... Check bit switch element array, 8 ... Parity check circuit, 9 ...
Activation circuit, 91 ... Shift register, 92, 93 ...
AND gate, 94 ... Inverter, 95 ... OR gate, 96 ... Parity check control terminal, 97 ...
Shift register input terminal, 97 ... Clock terminal, 99
...... Activation circuit output terminal, 100 ...... Circuit block output terminal.

Claims (2)

[Claims] 1. A plurality of circuit blocks, each having a logical function itself and having a signal input portion and a signal output portion, which are built in a substrate, and adjacent to a circuit block region formed by the plurality of circuit blocks. And a wiring region formed on the substrate, the circuit block region is composed of a set of a plurality of types of logic function elements, and the wiring region includes a signal input wiring group and a signal output wiring group that intersect with each other. The signal input wiring group is connected to the signal input section of each circuit block, the signal output wiring group is connected to the signal output section of each circuit block, and these connections are connected to the circuit block. Are performed in the wiring regions adjacent to each other, and switch elements are respectively provided at intersections of the signal input wiring group and the signal output wiring group in the wiring region. An integrated circuit in which an input / output relationship between circuit blocks is determined by controlling ON / OFF states of switch elements to construct a desired logic circuit, and the signal output wirings are activated one by one. A parity is provided with a circuit for determining whether the number of ON or OFF states of the switch elements on the activated signal output wiring is odd or even.
A semiconductor integrated circuit having a check circuit. 2. A check bit wiring is provided in parallel with the signal input wiring, and is turned on as a check bit at the intersection of the check bit wiring and each signal output wiring.
The semiconductor integrated circuit according to claim 1, further comprising a switch element in which an OFF state is written.