JPH0618208B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0618208B2 JPH0618208B2 JP62300957A JP30095787A JPH0618208B2 JP H0618208 B2 JPH0618208 B2 JP H0618208B2 JP 62300957 A JP62300957 A JP 62300957A JP 30095787 A JP30095787 A JP 30095787A JP H0618208 B2 JPH0618208 B2 JP H0618208B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- type
- manufacturing
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特に第一半導体基板上
に形成され、その一部を第二半導体材料で形成されてい
る半導体装置のオーミックコンタクト形成方法に関す
る。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an ohmic semiconductor device formed on a first semiconductor substrate, a part of which is formed of a second semiconductor material. The present invention relates to a contact forming method.
従来、第一半導体基板上に、その一部を第二半導体材料
を用いて形成された半導体装置は、装置製造工程中、前
記第二半導体が表面に出る構造となっているため、配線
などの工程において、第一半導体及び第二半導体のそれ
ぞれに適した配線材料や方法を用いて別々に行ってい
た。Conventionally, a semiconductor device, a part of which is formed on a first semiconductor substrate using a second semiconductor material, has a structure in which the second semiconductor is exposed on the surface during the device manufacturing process, and therefore, wiring etc. In the process, wiring materials and methods suitable for the first semiconductor and the second semiconductor are separately used.
上述の従来法では、例えば配線工程は、第一半導体及び
第二半導体に対して別々に行わなければならず、シリコ
ンの半導体装置のように、一度の配線工程で良いものに
比べ製造工程が複雑になる。また、製造工程中、第二半
導体が表面に出るため、第二半導体による不純物汚染が
問題となり、第二半導体使用後は第一半導体プロセスラ
インを使用できない。さらに、第二半導体材料が第一半
導体材料に比べオーミックコンタクトが取りにくい場合
は、装置の電気的特性が不安定になるという欠点があっ
た。In the above-mentioned conventional method, for example, the wiring process has to be performed separately for the first semiconductor and the second semiconductor, and the manufacturing process is complicated as compared with a semiconductor device made of silicon that requires only one wiring process. become. In addition, since the second semiconductor is exposed on the surface during the manufacturing process, impurity contamination by the second semiconductor becomes a problem, and the first semiconductor process line cannot be used after the second semiconductor is used. Further, when the second semiconductor material is less likely to make an ohmic contact than the first semiconductor material, the electrical characteristics of the device are unstable.
本発明の目的は上記問題点を解消した半導体装置の製造
方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device that solves the above problems.
本考案は第一半導体基板上の一部に第二半導体を有する
半導体装置を製造するに際し、n又はp形の前記第二半
導体上に、第一半導体膜を形成する工程と、前記第一半
導体膜と前記第二半導体との界面に、前記第二半導体と
同じ導電型となる不純物をイオン注入する工程と、前記
第一及び第二半導体で形成された部分に同時に電極を形
成する工程とを含むことを特徴とする半導体装置の製造
方法である。According to the present invention, in manufacturing a semiconductor device having a second semiconductor on a part of a first semiconductor substrate, a step of forming a first semiconductor film on the n- or p-type second semiconductor, A step of ion-implanting an impurity having the same conductivity type as that of the second semiconductor into an interface between the film and the second semiconductor, and a step of simultaneously forming an electrode in a portion formed by the first and second semiconductors. A method of manufacturing a semiconductor device, comprising:
第二半導体上に基板と同じ第一半導体膜を有することに
より、第二半導体は表面に露出することなく、第二半導
体による不純物汚染がなく、第一半導体のプロセスライ
ンが使用でき、第二半導体の配線を第一半導体の配線と
別に行う必要がない。一括配線によりプロセスが簡略化
できる。また、第二半導体と第一半導体の界面に第一半
導体と導電型になる不純物をイオン注入することにより
界面の自然酸化膜がミキシングされ。エレクトロンのバ
リアを除去できる。しかも、界面の第二半導体側が高濃
度不純物を含むため、オーミックコンタクトがとりやす
く、コンタクト抵抗を下げることができる。By having the same first semiconductor film as the substrate on the second semiconductor, the second semiconductor is not exposed on the surface, there is no impurity contamination by the second semiconductor, and the process line of the first semiconductor can be used. It is not necessary to perform the wiring of (1) separately from the wiring of the first semiconductor. The process can be simplified by batch wiring. In addition, the native oxide film on the interface is mixed by ion-implanting impurities that become conductive type with the first semiconductor into the interface between the second semiconductor and the first semiconductor. The electron barrier can be removed. Moreover, since the second semiconductor side of the interface contains high-concentration impurities, ohmic contact is easily made and contact resistance can be reduced.
以下に本発明の実施例を図によって説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図(a)〜(c)は本発明の製造方法を説明するためのシ
リコンヘテロバイポーラの一実施例である。FIGS. 1 (a) to 1 (c) show an embodiment of a silicon heterobipolar for explaining the manufacturing method of the present invention.
第1図(a)において、比抵抗10Ωcmのp形シリコン基板
1上に、イオン注入により、リン及びボロンをそれぞれ
1×1012/cm2、150KeV及び1×1014/cm2、30KeV注入
し、これをアニールして、n形コレクタ2及びp形ベー
ス3を形成したのち、酸化膜4を堆積し、エミッタの窓
明けををおこなって、エネルギーギャップの広いエミッ
タ材料であるn形の炭化珪素をシラン、プロパン、フォ
スフィン及びキャリアガスとして水素を用い、CVD 法で
気相成長させ、n形エミッタ6を形成する。次に、第1
図(b)のようにポリシリコンによるシリコン膜7を1000
Å堆積し、炭化珪素とポリシリコン間のエレクトロンの
バリアをエレクトロンがトンネルできるように、界面に
1×1014/cm2のリンを注入し、ラピッドサーマルアニ
ールを900 ℃、5秒間窒素中で行う。その後、第1図
(c)に示すようにベース、コレクタ、エミッタのコンタ
クトホール形成し、配線8を同時に行う。In FIG. 1 (a), phosphorus and boron are implanted into a p-type silicon substrate 1 having a specific resistance of 10 Ωcm by ion implantation at 1 × 10 12 / cm 2 , 150 KeV and 1 × 10 14 / cm 2 , 30 KeV, respectively. After this is annealed to form an n-type collector 2 and a p-type base 3, an oxide film 4 is deposited to open the window of the emitter, and n-type silicon carbide which is an emitter material with a wide energy gap is formed. Is vapor-deposited by a CVD method using silane, propane, phosphine and hydrogen as a carrier gas to form an n-type emitter 6. Then the first
As shown in Figure (b), the silicon film 7 made of polysilicon is
Å Deposit 1x10 14 / cm 2 of phosphorus at the interface so that electrons can tunnel the electron barrier between silicon carbide and polysilicon, and perform rapid thermal annealing at 900 ° C for 5 seconds in nitrogen. . After that, Fig. 1
As shown in (c), base, collector, and emitter contact holes are formed, and wiring 8 is performed at the same time.
また、エミッタ材料をエピ成長する場合は、エミッタ膜
形成後、シリコン膜をエピ成長し、上述のように不純物
をイオン注入することもできる。When the emitter material is epitaxially grown, the silicon film may be epitaxially grown after the emitter film is formed and the impurities may be ion-implanted as described above.
以上のように、本発明によれば第一半導体基板上の一部
に第二半導体材料を用いて形成された半導体装置の製造
にあたり、第一半導体のプロセスを使用できるため、プ
ロセスの簡易化に優れた効果を得ることができる。As described above, according to the present invention, since the process of the first semiconductor can be used in the manufacture of the semiconductor device formed by using the second semiconductor material on a part of the first semiconductor substrate, the process can be simplified. An excellent effect can be obtained.
第1図(a)〜(c)は本発明の一実施例の製造方法を工程順
に示す断面図である。 1……シリコン基板、2……n形コレクタ 3……p形ベース、4,5……酸化膜 6……n形エミッタ、7……シリコン膜 8……配線1 (a) to 1 (c) are cross-sectional views showing a method of manufacturing an embodiment of the present invention in the order of steps. 1 ... Silicon substrate, 2 ... N-type collector 3 ... P-type base, 4,5 ... Oxide film 6 ... N-type emitter, 7 ... Silicon film 8 ... Wiring
Claims (1)
する半導体装置を製造するに際し、n又はp形の前記第
二半導体上に、第一半導体膜を形成する工程と、前記第
一半導体膜と前記第二半導体との界面に、前記第二半導
体と同じ導電型となる不純物をイオン注入する工程と、
前記第一及び第二半導体で形成された部分に同時に電極
を形成する工程とを含むことを特徴とする半導体装置の
製造方法。1. When manufacturing a semiconductor device having a second semiconductor on a part of a first semiconductor substrate, a step of forming a first semiconductor film on the second semiconductor of n-type or p-type; A step of ion-implanting an impurity having the same conductivity type as the second semiconductor into an interface between the one semiconductor film and the second semiconductor;
And a step of simultaneously forming an electrode on a portion formed of the first and second semiconductors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300957A JPH0618208B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300957A JPH0618208B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01143262A JPH01143262A (en) | 1989-06-05 |
| JPH0618208B2 true JPH0618208B2 (en) | 1994-03-09 |
Family
ID=17891118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62300957A Expired - Lifetime JPH0618208B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618208B2 (en) |
-
1987
- 1987-11-27 JP JP62300957A patent/JPH0618208B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01143262A (en) | 1989-06-05 |
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