JPH0618209B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0618209B2 JPH0618209B2 JP62300958A JP30095887A JPH0618209B2 JP H0618209 B2 JPH0618209 B2 JP H0618209B2 JP 62300958 A JP62300958 A JP 62300958A JP 30095887 A JP30095887 A JP 30095887A JP H0618209 B2 JPH0618209 B2 JP H0618209B2
- Authority
- JP
- Japan
- Prior art keywords
- iii
- silicon
- compound semiconductor
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 150000001875 compounds Chemical class 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000470 constituent Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特にシリコン基板上に
形成された半導体装置の一部をIII−Ｖ族化合物半導体
材料で形成されている半導体装置のオーミックコンタク
ト形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor in which a part of the semiconductor device formed on a silicon substrate is made of a III-V group compound semiconductor material. The present invention relates to a method for forming an ohmic contact of a device.
従来、シリコン基板上にその一部をIII−Ｖ族化合物半
導体材料を用いて形成された半導体装置は、装置製造工
程中、III−Ｖ族化合物半導体が表面に出る構造となっ
ているため、配線などの工程において、シリコン及びII
I−Ｖ族化合物半導体のそれぞれに適した配線材料や方
法を用いて別々に行っていた。Conventionally, a semiconductor device partially formed on a silicon substrate by using a III-V group compound semiconductor material has a structure in which a III-V group compound semiconductor appears on the surface during a device manufacturing process. In the process such as
Wiring materials and methods suitable for each of the IV compound semiconductors were used separately.
上述の従来法では、例えば配線工程はシリコン及びIII
−Ｖ族化合物半導体に対して別々に行わなければなら
ず、シリコンの半導体装置のように、一度の配線工程で
良いものに比べ製造工程が複雑になる。また、製造工程
中、III−Ｖ族化合物半導体が表面に出るため、III−Ｖ
族化合物半導体による不純物汚染が問題となり、III−
Ｖ族化合物半導体使用後はシリコンプロセスラインを使
用できない。さらに、III−Ｖ族化合物半導体材料がシ
リコン材料に比べオーミックコンタクトが取りにくい場
合は、装置の電気的特性が不安定になるという欠点があ
った。In the above-mentioned conventional method, for example, the wiring process is performed using silicon and III.
Since it has to be performed separately for the group-V compound semiconductor, the manufacturing process is more complicated than that required for a single wiring process such as a silicon semiconductor device. In addition, since the III-V group compound semiconductor appears on the surface during the manufacturing process,
Contamination of impurities by group compound semiconductors became a problem, and III-
The silicon process line cannot be used after the group V compound semiconductor is used. Further, when the III-V compound semiconductor material is less likely to make ohmic contact than the silicon material, there is a drawback that the electrical characteristics of the device become unstable.
本発明の目的は上記問題点を解消した半導体装置の製造
方法を提供することにある。An object of the present invention is to provide a method of manufacturing a semiconductor device that solves the above problems.
本発明はシリコン基板上に形成された半導体装置の一部
がIII−Ｖ族化合物半導体で形成されている半導体装置
において、ｎ又はｐ形の前記III−Ｖ族化合物半導体上
に、シリコン膜を形成する工程と、前記シリコン膜と前
記III−Ｖ族化合物半導体界面に、前記III−Ｖ族化合物
半導体の構成元素のうち、ｎ又はｐ形を形成する不純物
であるシリコンがはいるべきでない格子位置の元素をイ
オン注入する工程と、前記シリコン及びIII−Ｖ族化合
物半導体で形成された部分に、同時に電極を形成する工
程とを含むことを特徴とする半導体装置の製造方法であ
る。The present invention is a semiconductor device in which a part of the semiconductor device formed on a silicon substrate is formed of a III-V group compound semiconductor, and a silicon film is formed on the n- or p-type III-V group compound semiconductor. Of the constituent elements of the III-V group compound semiconductor, silicon, which is an impurity forming the n-type or the p-type, should not enter the interface between the silicon film and the III-V group compound semiconductor. A method of manufacturing a semiconductor device, comprising: a step of ion-implanting an element; and a step of simultaneously forming an electrode in a portion formed of the silicon and the III-V group compound semiconductor.
III−Ｖ族化合物半導体上に基板と同じシリコン膜を有
することにより、III−Ｖ族化合物半導体は表面に露出
することがなく、III−Ｖ族化合物半導体による不純物
汚染が阻止され、シリコンのプロセスラインが使用で
き、III−Ｖ族化合物半導体の配線をシリコンの配線と
別に行う必要がない。一括配線によりプロセスが簡略化
できる。また、III−Ｖ族化合物半導体とシリコンの界
面に、III−Ｖ族化合物半導体の構成元素のうち、ｎ又
はｐ形を形成している不純物であるシリコンがはいるべ
きでない格子位置の元素をイオン注入することにより界
面の自然酸化膜がミキシングされ、エレクトロンのバリ
アを除去できる。しかも、界面の化合物半導体側におい
て、シリコンがはいるべきでない格子位置の元素が過剰
になるため、シリコンがより効果的に本来入るべき格子
位置にはいり、界面のキャリア濃度を高くすることがで
き、オーミックコンタクトがとりやすく、コンタクト抵
抗を下げることができる。By having the same silicon film as the substrate on the III-V compound semiconductor, the III-V compound semiconductor is not exposed on the surface, impurity contamination by the III-V compound semiconductor is prevented, and a silicon process line is provided. Can be used, and it is not necessary to form the wiring of the III-V group compound semiconductor separately from the wiring of silicon. The process can be simplified by batch wiring. In addition, at the interface between the III-V compound semiconductor and silicon, among the constituent elements of the III-V compound semiconductor, an element at a lattice position where silicon, which is an impurity forming the n-type or p-type, should not enter is ionized. By injecting, the natural oxide film on the interface is mixed, and the electron barrier can be removed. Moreover, on the compound semiconductor side of the interface, the elements at the lattice positions where silicon should not enter become excessive, so that silicon can more effectively enter the lattice positions where it should originally enter, and the carrier concentration at the interface can be increased. It is easy to make ohmic contact and the contact resistance can be reduced.
以下に本発明の実施例を図によって説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図(a)〜(c)は本発明の製造方法を説明するためのシ
リコンヘテロバイポーラの一実施例である。FIGS. 1 (a) to 1 (c) show an embodiment of a silicon heterobipolar for explaining the manufacturing method of the present invention.
第１図(a)において、比抵抗10Ωcmのｐ形シリコン基板
１上に、イオン注入により、リン及びボロンをそれぞれ
１×1012/cm2、150KeV及び１×1014/cm2、30KeV注入
し、これをアニールして、ｎ形コレクタ２及びｐ形ベー
ス３を形成したのち、酸化膜４を5000Å堆積し、エミッ
タの窓明けをを行う。次いで、第１図(b)のようにエミ
ッタ材料であるｎ形のガリウムヒ素をエピ成長し、ｎ形
エミッタ５を形成後、シリコン膜６をエピ成長により30
0 Å行い、エミッタ形成を行う。ｎ形エミッタ５のガリ
ウムヒ素とシリコン膜６との界面に濃度のピークがくる
ようにヒ素のイオン注入を５×1015/cm2行い、ラピッド
・サーマル・アニールを900 ℃、５秒行う。その後、第
１図(c)に示すようにパッシベーション酸化膜７を5000
Å堆積し、ベース、コレクタ、エミッタのコンタクトホ
ール形成、配線８を同時に行う。In FIG. 1 (a), phosphorus and boron are implanted into a p-type silicon substrate 1 having a specific resistance of 10 Ωcm by ion implantation at 1 × 10 12 / cm 2 , 150 KeV and 1 × 10 14 / cm 2 , 30 KeV, respectively. After this is annealed to form the n-type collector 2 and the p-type base 3, an oxide film 4 is deposited at 5000 Å to open the emitter window. Then, as shown in FIG. 1 (b), n-type gallium arsenide, which is an emitter material, is epitaxially grown, and after the n-type emitter 5 is formed, the silicon film 6 is epitaxially grown to 30 nm.
Perform 0 Å to form the emitter. Ion implantation of arsenic is performed at 5 × 10 15 / cm 2 so that a concentration peak appears at the interface between the gallium arsenide of the n-type emitter 5 and the silicon film 6, and rapid thermal annealing is performed at 900 ° C. for 5 seconds. After that, as shown in FIG. 1 (c), the passivation oxide film 7 is removed to 5000
Å Deposit, form contact holes for base, collector and emitter, and perform wiring 8 at the same time.
以上のように、本発明によるときにはシリコン基板上の
一部に化合物半導体材料を用いて形成された半導体装置
の製造にあたり、シリコンのプロセスを使用できるた
め、製造プロセスの簡易化、オーミックコンタクトの安
定化に優れた効果を得ることができる。As described above, according to the present invention, since a silicon process can be used in manufacturing a semiconductor device formed by using a compound semiconductor material on a part of a silicon substrate, the manufacturing process can be simplified and ohmic contact can be stabilized. The excellent effect can be obtained.
第１図(a)〜(c)は本発明の一実施例の製造方法を工程順
に示す断面図である。 １……シリコン基板、２……ｎ形コレクタ ３……ｐ形ベース、4,7……酸化膜 ５……ｎ形エミッタ、６……シリコン膜 ８……配線1 (a) to 1 (c) are cross-sectional views showing a method of manufacturing an embodiment of the present invention in the order of steps. 1 ... silicon substrate, 2 ... n type collector 3 ... p type base, 4,7 ... oxide film 5 ... n type emitter, 6 ... silicon film 8 ... wiring
Claims (1)
一部がIII−Ｖ族化合物半導体で形成されている半導体
装置において、ｎ又はｐ形の前記III−Ｖ族化合物半導
体上に、シリコン膜を形成する工程と、前記シリコン膜
と前記III−Ｖ族化合物半導体界面に、前記III−Ｖ族化
合物半導体の構成元素のうち、ｎ又はｐ形を形成する不
純物であるシリコンがはいるべきでない格子位置の元素
をイオン注入する工程と、前記シリコン及びIII−Ｖ族
化合物半導体で形成された部分に、同時に電極を形成す
る工程とを含むことを特徴とする半導体装置の製造方
法。1. A semiconductor device in which a part of the semiconductor device formed on a silicon substrate is formed of a III-V group compound semiconductor, wherein a silicon film is formed on the n- or p-type III-V group compound semiconductor. And a lattice in which silicon, which is an impurity forming the n-type or the p-type among the constituent elements of the III-V group compound semiconductor, should not be introduced at the interface between the silicon film and the III-V group compound semiconductor. A method of manufacturing a semiconductor device, comprising: a step of ion-implanting an element at a position; and a step of simultaneously forming an electrode on a portion formed of the silicon and the III-V group compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300958A JPH0618209B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300958A JPH0618209B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01143263A JPH01143263A (en) | 1989-06-05 |
| JPH0618209B2 true JPH0618209B2 (en) | 1994-03-09 |
Family
ID=17891130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62300958A Expired - Lifetime JPH0618209B2 (en) | 1987-11-27 | 1987-11-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618209B2 (en) |
-
1987
- 1987-11-27 JP JP62300958A patent/JPH0618209B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01143263A (en) | 1989-06-05 |
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