JPH0618238B2 - Method of forming flattened multilayer wiring - Google Patents
Method of forming flattened multilayer wiringInfo
- Publication number
- JPH0618238B2 JPH0618238B2 JP27452185A JP27452185A JPH0618238B2 JP H0618238 B2 JPH0618238 B2 JP H0618238B2 JP 27452185 A JP27452185 A JP 27452185A JP 27452185 A JP27452185 A JP 27452185A JP H0618238 B2 JPH0618238 B2 JP H0618238B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- multilayer wiring
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、平坦化多層配線の形成法に関し、特に平坦な
層間絶縁膜を形成する方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a planarized multilayer wiring, and particularly to a method for forming a flat interlayer insulating film.
高集積、高密度化半導体装置においては、金属多層配線
構造の採用が必須である。In a highly integrated and high-density semiconductor device, it is essential to adopt a metal multilayer wiring structure.
例えば、第２図に示すように、トランジスタ等の能動素
子部を形成したシリコン基板２０１上に、SiO2等の絶縁
膜２０２を介してＡｌ等からなる第１の金属配線２０３
を形成し、更に層間絶縁膜２０４を介して第２金属配線
２０５を形成する多層配線構造が用いられる。For example, as shown in FIG. 2, a first metal wiring 203 made of Al or the like is formed on a silicon substrate 201 on which an active element portion such as a transistor is formed, with an insulating film 202 such as SiO 2 interposed therebetween.
And a second metal wiring 205 is further formed via the interlayer insulating film 204.
上記したように、絶縁層を介して多層配線を形成する場
合、特に、第１の金属配線２０３の端部２０３ａの上に
形成される層間絶縁膜２０４の被覆性（ステップカバレ
ッジ）が悪くなり、この段差部分において第２の金属配
線層が薄くなり、断線を生じやすい欠点がある。As described above, when the multilayer wiring is formed via the insulating layer, the covering property (step coverage) of the interlayer insulating film 204 formed on the end portion 203a of the first metal wiring 203 is deteriorated, The second metal wiring layer becomes thin in this step portion, and there is a drawback that disconnection is likely to occur.
なお、被覆性改善のために層間絶縁膜の平坦化対策がと
られているが、従来の方法では高温による素子特性変
化，配線の劣化，絶縁膜の特性不良等何れかの問題点を
含み優れた平坦化多層配線の形成法は得られていない。Although measures are taken to flatten the interlayer insulating film in order to improve the covering property, the conventional method is superior in that it includes any problems such as changes in device characteristics due to high temperature, deterioration of wiring, and defective insulating film characteristics. A method for forming a flattened multilayer wiring has not been obtained.
本発明の目的は、平坦性が優れ、断線がない多層配線構
造を容易に形成することが可能な平坦化多層配線の形成
法を提供することにある。It is an object of the present invention to provide a method for forming a flattened multi-layered wiring, which has excellent flatness and can easily form a multi-layered wiring structure free from disconnection.
本発明の平坦化多層配線の形成法は、絶縁膜並びに電極
の形成された半導体基板の一主面に層間絶縁膜，金属配
線により平坦性の優れた多層配線を形成する平坦化多層
配線の形成法において、一般式Rn-Si（OR′）
４−ｎ（Ｒ：炭素数１〜６のアルキル基，Ｒ′：炭素数
０〜４のアルキル基，ｎ：０，１，２，３）からなる樹
脂ガラス溶液を前記半導体基板に塗布し、酸素を含む雰
囲気中で５００℃以上の温度で熱処理し、シリコン酸化
膜を形成し、該シリコン酸化膜を層間絶縁膜として多層
配線を形成することにより構成される。The method for forming a flattened multi-layered wiring according to the present invention is a method for forming a flattened multi-layered wiring, in which a multi-layered wiring excellent in flatness is formed by an interlayer insulating film and a metal wiring on one main surface of a semiconductor substrate on which an insulating film and electrodes are formed. Method, the general formula Rn-Si (OR ')
4-n (R: alkyl group having 1 to 6 carbon atoms, R ': alkyl group having 0 to 4 carbon atoms, n: 0, 1, 2, 3) is applied to the semiconductor substrate, The heat treatment is performed at a temperature of 500 ° C. or higher in an atmosphere containing oxygen to form a silicon oxide film, and the silicon oxide film is used as an interlayer insulating film to form a multilayer wiring.
なお、(C6H5-Si-O)n溶液膜を酸素雰囲気中で５５０℃で
１２０分間酸化分解することにより均一なSiO2膜が得ら
れることは、応用物理学会講演予稿集，P375,31p-G-6
（昭和６０年３月）に発表されている。The fact that a uniform SiO 2 film can be obtained by oxidatively decomposing a (C 6 H 5 —Si—O) n solution film in an oxygen atmosphere at 550 ° C. for 120 minutes is described in Proceedings of the Japan Society of Applied Physics, P375, 31p-G-6
It was announced in (March 1985).
本発明者は一般式Rn-Si（OR′）４−ｎからなる樹脂ガ
ラス溶液としてはCH3・Si(OH)3,C2H5・Si(OH)3,C6H5・Si(O
H)3,CH3・Si(OC2H5)3,C2H5・Si(OC2H5)3等のうちの少なく
とも１種類と、エチルセロソルブ，ブチルセロソルブ等
の溶媒と混合した溶液につき検討した。なお樹脂ガラス
膜は溶液の塗布により平坦化された樹脂ガラス膜が形成
でき、この膜を５００℃以上の酸素雰囲気中の加熱によ
り酸化分解すれば完全にSiO2膜になっていることを赤外
吸収スペクトルにより確認し、しかも均一で良質の絶縁
膜であることがわかった。The present inventors have as a general formula Rn-Si (OR ') resin glass solution comprising 4-n CH 3 · Si ( OH) 3, C 2 H 5 · Si (OH) 3, C 6 H 5 · Si ( O
H) 3 , CH 3 · Si (OC 2 H 5 ) 3 , C 2 H 5 · Si (OC 2 H 5 ) 3 etc. and a solution mixed with a solvent such as ethyl cellosolve or butyl cellosolve investigated. It should be noted that the resin glass film can be formed into a flattened resin glass film by applying a solution, and if this film is oxidatively decomposed by heating in an oxygen atmosphere at 500 ° C. or higher, it can be said to be a completely SiO 2 film. It was confirmed by an absorption spectrum that it was found to be a uniform and good-quality insulating film.
すなわち、塗布により平坦な膜ができ、これを５００℃
で酸化分解すれば平坦化された均一良質なSiO2膜が形成
できるのでこれを多層配線の層間絶縁膜として用いれ
ば、従来問題であった素子特性の変化，配線の劣化，絶
縁膜の特性不良の問題を解決することができる。That is, a flat film is formed by coating,
If it is used as an interlayer insulating film for multi-layer wiring, it is possible to form a flat and uniform SiO 2 film by oxidative decomposition. Can solve the problem.
次に、本発明の実施例について図面を参照して説明す
る。第１図(a)〜(d)は本発明の一実施例を説明するため
に工程順に示した多層配線構造の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (d) are cross-sectional views of a multilayer wiring structure shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図(a)に示すように、半導体素子能動部が形
成され、さらに絶縁膜１０２を介した多結晶シリコン電
極１０３が形成されたシリコン基板１０１の表面に、CH
3-Si(OH)3とC6H5-Si(OH)3を主成分とする樹脂ガラス溶
液を回転塗布し、２４０℃で３０分間酸素雰囲気中で熱
処理し、約２μｍの厚さの樹脂ガラス膜を形成する。こ
のとき形成される樹脂ガラス膜は表面が平坦となる。次
に、７００℃で１時間酸素雰囲気中で酸化分解すること
によって、約1.5μｍ厚の第１のシリコン酸化膜１０４
が形成される、この酸化膜は前述したように、平坦性，
均質性等優れた膜である。First, as shown in FIG. 1 (a), CH
Resin glass solution containing 3 -Si (OH) 3 and C 6 H 5 -Si (OH) 3 as main components is spin-coated and heat-treated in an oxygen atmosphere at 240 ° C for 30 minutes to give a resin having a thickness of about 2 μm. Form a glass film. The resin glass film formed at this time has a flat surface. Next, the first silicon oxide film 104 having a thickness of about 1.5 μm is formed by oxidative decomposition at 700 ° C. for one hour in an oxygen atmosphere.
As described above, this oxide film has a flatness,
It is a film with excellent homogeneity.
次に、第１図(b)に示すように、フォトエッチング法に
より、さきに形成されたシリコン酸化膜１０４に下層の
多結晶シリコン電極に達するスルーホール１０５を形成
する。Next, as shown in FIG. 1B, a through hole 105 reaching the lower polycrystalline silicon electrode is formed in the previously formed silicon oxide film 104 by photoetching.
次に、第１図(c)に示すように、気相成長法による、タ
ングステン膜を約１μｍの厚さで形成し、フォトエッチ
ングにより第１の金属配線１０６を形成する。Next, as shown in FIG. 1C, a tungsten film is formed to a thickness of about 1 μm by a vapor phase epitaxy method, and a first metal wiring 106 is formed by photoetching.
次に、第１図(d)に示すように、樹脂ガラス膜を酸化分
解して形成した第２のシリコン酸化膜１０７，第２のス
ルーホール１０８，第２の金属配線１０９を形成する。
以上により２層配線構造体が完成する。Next, as shown in FIG. 1D, a second silicon oxide film 107 formed by oxidizing and decomposing the resin glass film, a second through hole 108, and a second metal wiring 109 are formed.
The two-layer wiring structure is completed as described above.
以下、必要により第２の金属配線１０９上に樹脂ガラス
を酸化分解して形成した第３のシリコン酸化膜を設けた
後、前述した第１図(b)〜(c)の工程をくり返すことによ
り３層以上の平坦化された多層配線構造体を得ることが
できる。Thereafter, if necessary, a third silicon oxide film formed by oxidizing and decomposing resin glass is provided on the second metal wiring 109, and then the steps of FIGS. 1B to 1C described above are repeated. Thereby, a flattened multilayer wiring structure having three or more layers can be obtained.
なお、実施例では金属配線膜としてタングステン膜を用
いたが本発明の層間絶縁膜は５００℃以上で平坦均一な
SiO2膜が形成できるのでアルミニウム膜に容易に適用で
きる。Although the tungsten film is used as the metal wiring film in the embodiment, the interlayer insulating film of the present invention is flat and uniform at 500 ° C. or higher.
Since a SiO 2 film can be formed, it can be easily applied to an aluminum film.
以上説明したように、本発明に基ずき、塗布・成膜した
樹脂ガラス膜を酸化分解して形成したシリコン酸化膜を
層間絶縁膜として用いることにより平坦性の優れた断線
の全くない多層配線構造体を容易に形成することが可能
となり半導体装置の高集積化に大きな効果をもたらす。As described above, according to the present invention, by using a silicon oxide film formed by oxidizing and decomposing a coated / deposited resin glass film as an interlayer insulating film, a multilayer wiring having excellent flatness and no breakage The structure can be easily formed, which has a great effect on high integration of the semiconductor device.
第１図(a)〜(d)は本発明の一実施例を説明するために工
程順に示した多層配線構造体の断面図、第２図は従来の
多層配線構造体の断面図である。 １０１……シリコン基板、１０２……絶縁膜、１０３…
…多結晶シリコン電極、１０４……第１のシリコン酸化
膜、１０５……第１のスルーホール、１０６……第１の
金属配線、１０７……第２のシリコン酸化膜、１０８…
…第２のスルーホール、１０９……第２の金属配線、２
０１……シリコン基板、２０２……絶縁膜、２０３……
第１の金属配線、２０３ａ……第１の金属配線の端部、
２０４……層間絶縁膜、２０５…第２の金属配線。1 (a) to 1 (d) are sectional views of a multilayer wiring structure shown in order of steps for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional multilayer wiring structure. 101 ... Silicon substrate, 102 ... Insulating film, 103 ...
... polycrystalline silicon electrode, 104 ... first silicon oxide film, 105 ... first through hole, 106 ... first metal wiring, 107 ... second silicon oxide film, 108 ...
... second through hole, 109 ... second metal wiring, 2
01 ... Silicon substrate, 202 ... Insulating film, 203 ...
First metal wiring, 203a ... an end portion of the first metal wiring,
204 ... interlayer insulating film, 205 ... second metal wiring.
Claims (1)
の一主面に層間絶縁膜，金属配線により平坦性の優れた
多層配線を形成する平坦化多層配線の形成法において、
一般式Rn-Si（OR′）４−ｎ（Ｒ：炭素数１〜６のアル
キル基，Ｒ′：炭素数０〜４のアルキル基，ｎ：０，
１，２，３）からなる樹脂ガラス溶液を前記半導体基板
に塗布し、酸素を含む雰囲気中で５００℃以上の温度で
熱処理し、シリコン酸化膜を形成し、該シリコン酸化膜
を層間絶縁膜として多層配線を形成することを特徴とす
る平坦化多層配線の形成法。1. A method for forming a flattened multi-layered wiring, which comprises forming a multi-layered wiring excellent in flatness by an inter-layer insulating film and a metal wiring on one main surface of a semiconductor substrate on which an insulation film and electrodes are formed.
General formula Rn-Si (OR ') 4-n (R: alkyl group having 1 to 6 carbon atoms, R': alkyl group having 0 to 4 carbon atoms, n: 0,
1, 2, 3) is applied to the semiconductor substrate and heat-treated at a temperature of 500 ° C. or higher in an atmosphere containing oxygen to form a silicon oxide film, and the silicon oxide film is used as an interlayer insulating film. A method of forming a flattened multilayer wiring, which comprises forming a multilayer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27452185A JPH0618238B2 (en) | 1985-12-05 | 1985-12-05 | Method of forming flattened multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27452185A JPH0618238B2 (en) | 1985-12-05 | 1985-12-05 | Method of forming flattened multilayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62133736A JPS62133736A (en) | 1987-06-16 |
| JPH0618238B2 true JPH0618238B2 (en) | 1994-03-09 |
Family
ID=17542858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27452185A Expired - Lifetime JPH0618238B2 (en) | 1985-12-05 | 1985-12-05 | Method of forming flattened multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618238B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457626A (en) * | 1987-08-28 | 1989-03-03 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6461036A (en) * | 1987-09-01 | 1989-03-08 | Nec Corp | Manufacture of semiconductor device |
-
1985
- 1985-12-05 JP JP27452185A patent/JPH0618238B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62133736A (en) | 1987-06-16 |
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